Sharad Sinha

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 71

Top Topics

High Level Synthesis

Hardware Architecture

Cache Management

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Shubhayu Das, Nanditha P. Rao, Sharad Sinha
ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) (2024)
Enlai Li, Sharad Sinha, Wei Zhang
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. IEEE Trans. Very Large Scale Integr. Syst. 32 (8) (2024)
Pavitra Prakash Bhade, Joseph Paturel, Olivier Sentieys, Sharad Sinha
Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe). ACM Trans. Embed. Comput. Syst. 23 (4) (2024)
Akanksha Mishra, Sharad Sinha, Clint Pazhayidam George
Shielding against online harm: A survey on text analysis to prevent cyberbullying. Eng. Appl. Artif. Intell. 133 (2024)
Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA (2024)
Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. ICFPT (2023)
Prachi Kashikar, Olivier Sentieys, Sharad Sinha
Lossless Neural Network Model Compression Through Exponent Sharing. IEEE Trans. Very Large Scale Integr. Syst. 31 (11) (2023)
Vipin Gautam, Shitala Prasad, Sharad Sinha
YOLORe-IDNet: An Efficient Multi-camera System for Person-Tracking. CVIP (1) (2023)
Vipin Gautam, Shitala Prasad, Sharad Sinha
AaP-ReID: Improved Attention-Aware Person Re-identification. CoRR (2023)
Vipin Gautam, Shitala Prasad, Sharad Sinha
Joint-YODNet: A Light-weight Object Detector for UAVs to Achieve Above 100fps. CoRR (2023)
Sathi Sarveswara Reddy, Sharad Sinha, Wei Zhang
Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation. IEEE Trans. Computers 72 (7) (2023)
Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Vipin Gautam, Shitala Prasad, Sharad Sinha
Joint-YODNet: A Light-Weight Object Detector for UAVs to Achieve Above 100fps. CVIP (2) (2023)
Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. DATE (2023)
Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. FCCM (2023)
Vipin Gautam, Shitala Prasad, Sharad Sinha
YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking. CoRR (2023)
Sheikh K. Ghafoor, Sushil K. Prasad, Ashish Kuvelkar, Sharad Sinha, Satish Puri
Message from Workshop Chairs. HiPCW (2023)
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA (2023)
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR (2022)
Aditi Saxena, Sharad Sinha
Machine Learning Based Webcasting Analytics for Indian Elections - Reflections on Deployment. CVIP (2) (2022)
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR (2022)
Sharad Sinha
Workings of science: Is engineering applied science? Ubiquity 2022 (May) (2022)
Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
Attack Directories on ARM big.LITTLE Processors. ICCAD (2022)
Prachi Kashikar, Sharad Sinha, Ajeet Kumar Verma
Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware. AICAS (2021)
Risikesh RK, Sharad Sinha, Nanditha Rao
Variable Bit-Precision Vector Extension for RISC-V Based Processors. MCSoC (2021)
Prachi Kashikar, Sharad Sinha
Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format. ISQED (2021)
Pavitra Prakash Bhade, Sharad Sinha
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. MCSoC (2021)
Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. DAC (2021)
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD (2021)
Zhe Lin, Sharad Sinha, Wei Zhang
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (11) (2021)
Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod
A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs. Neural Process. Lett. 53 (3) (2021)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL (2020)
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (7) (2020)
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC (2020)
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. CoRR (2020)
Arish Sateesan, Sharad Sinha, Smitha K. G.
DASH: Design Automation for Synthesis and Hardware Generation for CNN. FPT (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power. CoRR (2020)
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. ACM Trans. Reconfigurable Technol. Syst. 13 (3) (2020)
Zhe Lin, Wei Zhang, Sharad Sinha
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA. CoRR (2020)
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR (2020)
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. CoRR (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. CoRR (2020)
Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. ASP-DAC (2020)
Zhe Lin, Sharad Sinha, Wei Zhang
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. FCCM (2019)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD (2019)
Ang Poh Keong, K. G. Smitha, Sharad Sinha
Smart Nation: Offline Public Transport Made Easy. ICITE (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA (2019)
Lim Boon Leng, Smitha K. G., Sharad Sinha
Smart Nation: Indoor Navigation for the Visually Impaired. ICITE (2019)
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC (2019)
Arish S, Sharad Sinha, Smitha K. G.
Optimization of Convolutional Neural Networks on Resource Constrained Devices. ISVLSI (2019)
Sharad Sinha, Clint P. George
Artificial intelligence for all using R programming language. AI Matters 5 (4) (2019)
Zhe Lin, Sharad Sinha, Wei Zhang
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (9) (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR (2019)
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE (2019)
Hao Liang, Sharad Sinha, Wei Zhang
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (2) (2018)
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. FPL (2018)
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. FCCM (2018)
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. ICCAD (2017)
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. 16 (1) (2017)
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD (2017)
Zhe Lin, Wei Zhang, Sharad Sinha
Decision tree based hardware power monitoring for run time dynamic power management in FPGA. FPL (2017)
Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang
PAAS: A system level simulator for heterogeneous computing architectures. FPL (2017)
Mohammad Tahghighi, Wei Zhang, Sharad Sinha
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. ISVLSI (2016)
Sharad Sinha, Wei Zhang
Low-Power FPGA Design Using Memoization-Based Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Mohammad Tahghighi, Sharad Sinha, Wei Zhang
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. ARC (2016)
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
HeteroSim: A heterogeneous CPU-FPGA simulator. FPL (2016)
Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. FPL (2015)
Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li
Hierarchical library based power estimator for versatile FPGAs. FPL (2015)
Sharad Sinha, Thambipillai Srikanthan
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. Int. J. Reconfigurable Comput. 2014 (2014)
Sharad Sinha, Thambipillai Srikanthan
Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective. ACM Trans. Design Autom. Electr. Syst. 20 (1) (2014)
Sharad Sinha, Thambipillai Srikanthan
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. Int. J. Reconfigurable Comput. 2014 (2014)
Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan
Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. J. Circuits Syst. Comput. 23 (9) (2014)
Dipanjan Bhowmik, Avijit Datta, Sharad Sinha
A Bit-Level Block Cipher Diffusion Analysis Test - BLDAT. FICTA (1) (2014)
Sharad Sinha, Thambipillai Srikanthan
Dataflow graph partitioning for high level synthesis. FPL (2012)
Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI (2011)