Udit Dhawan

Publication Activity (10 Years)

Years Active: 2011-2018
Publications (10 Years): 1

Top Topics

High Level Synthesis

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Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang
MARS: Memory Aware Reordered Source. CoRR (2018)
Udit Dhawan, André DeHon
Area-Efficient Near-Associative Memories on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7 (4) (2015)
Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon
Architectural Support for Software-Defined Metadata Processing. ASPLOS (2015)
Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon
PUMP: a programmable unit for metadata processing. HASP@ISCA (2014)
Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan
Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. J. Circuits Syst. Comput. 23 (9) (2014)
Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon
Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security. CCS (2013)
Udit Dhawan, André DeHon
Area-efficient near-associative memories on FPGAs. FPGA (2013)
Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David K. Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan
Hardware Support for Safety Interlocks and Introspection. SASO Workshops (2012)
Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI (2011)