Siew Kei Lam

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 20

Top Topics

Algorithmic Aspects

Corner Detection

Vehicular Networks

Top Venues

IEEE Trans. Intell. Transp. Syst.

J. Supercomput.

Publications

Yalan Wu, Jigang Wu, Long Chen, Bosheng Liu, Mianyang Yao, Siew Kei Lam
Share-Aware Joint Model Deployment and Task Offloading for Multi-Task Inference. IEEE Trans. Intell. Transp. Syst. 25 (6) (2024)
Yalan Wu, Jigang Wu, Mianyang Yao, Bosheng Liu, Long Chen, Siew Kei Lam
Two-Level Scheduling Algorithms for Deep Neural Network Inference in Vehicular Networks. IEEE Trans. Intell. Transp. Syst. 24 (9) (2023)
Appan Rakaraddi, Siew Kei Lam, Mahardhika Pratama, Marcus de Carvalho
Reinforced Continual Learning for Graphs. CoRR (2022)
Yidan Sun, Guiyuan Jiang, Siew Kei Lam, Peilan He
Predicting Traffic Congestion Evolution: A Deep Meta Learning Approach. IJCAI (2021)
Kuldeep Sharma, Nirmala Ramakrishnan, Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan
Evaluating the Merits of Ranking in Structured Network Pruning. ICDCS (2020)
Duvindu Piyasena, Miyuru Thathsara, Sathursan Kanagarajah, Siew Kei Lam, Meiqing Wu
Dynamically Growing Neural Network Architecture for Lifelong Deep Learning on the Edge. FPL (2020)
Sirin Haddad, Siew Kei Lam
Graph2Kernel Grid-LSTM: A Multi-Cued Model for Pedestrian Trajectory Prediction by Learning Adaptive Neighborhoods. CoRR (2020)
Jigang Wu, Yalan Wu, Guiyuan Jiang, Siew Kei Lam
Algorithms for Reconfiguring NoC-Based Fault-Tolerant Multiprocessor Arrays. J. Circuits Syst. Comput. 28 (7) (2019)
Sirin Haddad, Meiqing Wu, He Wei, Siew Kei Lam
Situation-Aware Pedestrian Trajectory Prediction with Spatio-Temporal Attention Model. CoRR (2019)
Dihao Ai, Guiyuan Jiang, Siew Kei Lam, Chengwu Li
Automatic Pixel-Level Pavement Crack Detection Using Information of Multi-Scale Neighborhoods. IEEE Access 6 (2018)
Phong Tran, Thinh Hung Pham, Siew Kei Lam, Meiqing Wu, Bhavan A. Jasani
Stream-Based ORB Feature Extractor with Dynamic Power Optimization. FPT (2018)
Manaar Alam, Debdeep Mukhopadhyay, Sai Praveen Kadiyala, Siew Kei Lam, Thambipillai Srikanthan
Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms. PROOFS (2018)
Jigang Wu, Zinan He, Yaoguo Zhang, Renfei Gao, Siew Kei Lam
General Algorithm for Fault-Tolerant Virtual Machine Assignments. ISPA/IUCC (2017)
Kratika Garg, Siew Kei Lam, Thambipillai Srikanthan, Vedika Agarwal
Real-time road traffic density estimation using block variance. WACV (2016)
Deshya Wijesundera, Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan
Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors. SCOPES (2016)
Renfei Gao, Jigang Wu, Guiyuan Jiang, Siew Kei Lam, Thambipillai Srikanthan
Reducing Access Latency in Virtual Machine Assignments. HPCC/SmartCity/DSS (2016)
Wenjun Shi, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan
Algorithms for bi-objective multiple-choice hardware/software partitioning. Comput. Electr. Eng. 50 (2016)
Jigang Wu, Ningjing Liu, Siew Kei Lam, Guiyuan Jiang
Shortest Partial Path First Algorithm for Reconfigurable Processor Array with Faults. Trustcom/BigDataSE/ISPA (2016)
Pon Nidhya Elango, Siew Kei Lam
Bounded iterative thresholding for lumen region detection in endoscopic images. ICARCV (2016)
Nirmala Ramakrishnan, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Enhanced low-complexity pruning for corner detection. J. Real Time Image Process. 12 (1) (2016)
Xu Wang, Jigang Wu, Guiyuan Jiang, Siew Kei Lam, Thambipillai Srikanthan
Fast Replica Placement and Update Strategies in Tree Networks. CCGRID (2015)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Rapid estimation of DSPs utilization for efficient high-level synthesis. DSP (2015)
Kratika Garg, Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
KnapSim - Run-time efficient hardware-software partitioning technique for FPGAs. SoCC (2015)
Guiyuan Jiang, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan, Jizhou Sun
Algorithmic aspects of graph reduction for hardware/software partitioning. J. Supercomput. 71 (6) (2015)
Nirmala Ramakrishnan, Thambipillai Srikanthan, Siew Kei Lam, Gauri Ravindra Tulsulkar
Adaptive Window Strategy for High-Speed and Robust KLT Feature Tracker. PSIVT (2015)
Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Nonparametric Technique Based High-Speed Road Surface Detection. IEEE Trans. Intell. Transp. Syst. 16 (2) (2015)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Rapid evaluation of custom instruction selection approaches with FPGA estimation. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7 (3) (2014)
Nirmala Ramakrishnan, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Mask-based non-maximal suppression with iterative pruning for low-complexity corner detection. ISIC (2014)
Jigang Wu, Guiyuan Jiang, Yuze Shen, Siew Kei Lam, Jizhou Sun, Thambipillai Srikanthan
Parallel reconfiguration algorithms for mesh-connected processor arrays. J. Supercomput. 69 (2) (2014)
Nirmala Ramakrishnan, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Automated thresholding for low-complexity corner detection. AHS (2014)
Wenjun Shi, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan
Algorithmic Aspects for Bi-Objective Multiple-Choice Hardware/Software Partitioning. PAAP (2014)
Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Stereo based ROIs generation for detecting pedestrians in close proximity. ITSC (2014)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control. J. Low Power Electron. 10 (3) (2014)
Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan, Tushar Shah
Vision-based pedestrian tracking system using color and motion cue. ISIC (2014)
Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan
Iris Recognition Using Stable Dark Features. J. Comput. 8 (1) (2013)
Yuanbo Zhu, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan
Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays. ISCAS (2013)
Jigang Wu, Pu Wang, Siew Kei Lam, Thambipillai Srikanthan
Efficient heuristic and tabu search for hardware/software partitioning. J. Supercomput. 66 (1) (2013)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Hardware-Software Codesign of EKF-Based Motor Control for Domain-Specific Reconfigurable Platform. ISED (2013)
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
FPGA-aware techniques for rapid generation of profitable custom instructions. Microprocess. Microsystems 37 (3) (2013)
Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Modelling communication overhead for accessing local memories in hardware accelerators. ASAP (2013)
Gaurav Mishra, Yan Lin Aung, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan
Real-Time Image Resizing Hardware Accelerator for Object Detection Algorithms. ISED (2013)
Yuanbo Zhu, Jigang Wu, Siew Kei Lam, Thambipillai Srikanthan
Reconfiguration Algorithms for Degradable VLSI Arrays with Switch Faults. ICPADS (2012)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. ReCoSoC (2012)
Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan
Iris Recognition of Defocused Images for Mobile phones. Int. J. Pattern Recognit. Artif. Intell. 26 (8) (2012)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Area-time estimation of C-based functions for design space exploration. FPT (2012)
Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan
Exploiting stable features for iris recognition of defocused images. ISCAS (2012)
Meiqing Wu, Nirmala Ramakrishnan, Siew Kei Lam, Thambipillai Srikanthan
Low-complexity pruning for accelerating corner detection. ISCAS (2012)
Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI (2011)
Lieu My Chuong, Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan, Chai-Soon Lim
Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration. PAAP (2011)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs. IEEE Trans. Computers 60 (5) (2011)
Bo Liu, Siew Kei Lam, Thambipillai Srikanthan, Weiqi Yuan
Utilizing Dark Features for Iris Recognition in Less Constrained Environments. PAAP (2011)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Compiler-assisted technique for rapid performance estimation of FPGA-based processors. SoCC (2011)
Alok Prakash, Siew Kei Lam, Christopher T. Clarke, Thambipillai Srikanthan
Instruction set customization for area-constrained FPGA designs. SoCC (2011)
Siew Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations. ARC (2010)
Song Yang, Siew Kei Lam, Thambipillai Srikanthan
An efficient edge and corner detector. ICARCV (2010)
Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan
Architecture-Aware Custom Instruction Generation for Reconfigurable Processors. ARC (2010)
Siew Kei Lam, Thambipillai Srikanthan
Accelerating shortest path computations in hardware. CASE (2010)
Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan
Performance estimation framework for FPGA-based processors. FPT (2010)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Selecting profitable custom instructions for reconfigurable processors. J. Syst. Archit. 56 (8) (2010)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Selecting Profitable Custom Instructions for Area-Time-Efficient Realization on Reconfigurable Architectures. IEEE Trans. Ind. Electron. 56 (10) (2009)
Siew Kei Lam, Thambipillai Srikanthan
Rapid design of area-efficient custom instructions for reconfigurable embedded processing. J. Syst. Archit. 55 (1) (2009)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection. ACIS-ICIS (2009)
Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan
Rapid design exploration framework for application-aware customization of soft core processors. FPL (2009)
Siew Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang
Run-time management of custom instructions on a partially reconfigurable architecture. Int. J. Inf. Commun. Technol. 2 (1/2) (2009)
Lieu My Chuong, Siew Kei Lam, Thambipillai Srikanthan
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA. IEEE International Workshop on Rapid System Prototyping (2009)
George Rosario Jagadeesh, Siew Kei Lam, Thambipillai Srikanthan
A Short Course on Implementing FPGA Based Digital Systems. ICPADS (2008)
Siew Kei Lam, Thambipillai Srikanthan
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. ASAP (2007)
Lieu My Chuong, Siew Kei Lam, Thambipillai Srikanthan
Rapid Area-Time Estimation Technique for Porting C-based Applications onto FPGA platforms. Scalable Comput. Pract. Exp. 8 (4) (2007)
Leipo Yan, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang
Energy Efficient Cache Tuning with Performance Bound. DELTA (2006)
Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke
Rapid generation of custom instructions using predefined dataflow structures. Microprocess. Microsystems 30 (6) (2006)
C. S. Lim, Siew Kei Lam, Hui Tian, Thambipillai Srikanthan
Efficient Architectures for Segmentation of Endoscopic Images in Micro-Robotic Auto Navigation Systems. Int. J. Humanoid Robotics 3 (4) (2006)
Siew Kei Lam, Bharathi N. Krishnan, Thambipillai Srikanthan
Efficient management of custom instructions for run-time reconfigurable instruction set processors. FPT (2006)
Siew Kei Lam, Mohammed Shoaib, Thambipillai Srikanthan
Modeling Arbitrator Delay-Area Dependencies in Customizable Instruction Set Processors. DELTA (2006)
Siew Kei Lam, Yun Deng, Thambipillai Srikanthan
Morphable Structures for Reconfigurable Instruction Set Processors. Asia-Pacific Computer Systems Architecture Conference (2005)
Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan
VLSI-efficient schemes for high-speed construction of tangent graph. Robotics Auton. Syst. 51 (4) (2005)
Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan
Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction. IEEE Trans. Ind. Electron. 51 (6) (2004)
Thambipillai Srikanthan, Siew Kei Lam, Mishra Suman
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System. IEEE Trans. Computers 53 (1) (2004)
Suchitra Sathyanarayana, Siew Kei Lam, Thambipillai Srikanthan
High-throughput image rotation using sign-prediction based redundant cordic algorithm. ICIP (2004)
K. H. Quek, Siew Kei Lam, N. K. Agrawal, Thambipillai Srikanthan
Architectural design and analysis toolbox to implement shortest path algorithms in hardware. ISCAS (3) (2003)
Hui Tian, Siew Kei Lam, Thambipillai Srikanthan
Implementing Otsu's thresholding process using area-time efficient logarithmic approximation unit. ISCAS (4) (2003)
Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan
Low cost logarithmic techniques for high-precision computations. ISCAS (5) (2003)
Hui Tian, Thambipillai Srikanthan, Vijayan K. Asari, Siew Kei Lam
Study on the Effect of Object to Camera Distance on Polynomial Expansion Coefficients in Barrel Distortion Correction. SSIAI (2002)
Siew Kei Lam, Thambipillai Srikanthan
Environment Modelling for Robot Navigation Using VLSI-Efficient Logarithmic Approximation Method. J. Intell. Robotic Syst. 35 (1) (2002)
Siew Kei Lam, Thambipillai Srikanthan, Nitin Goyal, Neeraj Tyagi
Incorporating area-time flexibility to a binary signed-digit adder. APCCAS (1) (2002)
Siew Kei Lam, Thambipillai Srikanthan
A linear approximation based hybrid approach for binary logarithmic conversion. Microprocess. Microsystems 26 (8) (2002)
Hui Tian, Siew Kei Lam, Thambipillai Srikanthan, Chip-Hong Chang
An efficient architecture for adaptive progressive thresholding. APCCAS (1) (2002)
C. S. Lim, Thambipillai Srikanthan, Vijayan K. Asari, Siew Kei Lam
Fuzzy-ART based image compression for hardware implementation. APCCAS (2) (2002)
Siew Kei Lam, Thambipillai Srikanthan
High-Speed Environment Representation Scheme for Dynamic Path Planning. J. Intell. Robotic Syst. 32 (3) (2001)
Siew Kei Lam, Thambipillai Srikanthan
Dynamic multicast routing in VLSI. Comput. Commun. 23 (11) (2000)