Wu Jigang

Publication Activity (10 Years)

Years Active: 2000-2014
Publications (10 Years): 0

Top Topics

Matching Algorithm

Top Venues

IPDPS Workshops

IEEE Trans. Parallel Distributed Syst.

Publications

Wu Jigang, Thambipillai Srikanthan, Guiyuan Jiang, Kai Wang
Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays. IEEE Trans. Parallel Distributed Syst. 25 (4) (2014)
Wu Jigang, Guiyuan Jiang, Yuanrui Zhang, Yuanbo Zhu
Algorithm for Communication Synchronization on Reconfigurable Processor Arrays with Faults. IPDPS Workshops (2012)
Guiyuan Jiang, Wu Jigang, Jizhou Sun
Efficient Reconfiguration Algorithm for Three-dimensional VLSI Arrays. IPDPS Workshops (2012)
Liying Yang, Guozhi Song, Wu Jigang
A Performance Evaluation of Cellular/WLAN Integrated Networks. PAAP (2011)
Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Amit Kumar Singh, Akash Kumar, Wu Jigang, Thambipillai Srikanthan
Communication-Aware Design Space Exploration for Efficient Run-Time MPSoC Management. PAAP (2011)
Samarth Kaushik, Amit Kumar Singh, Wu Jigang, Thambipillai Srikanthan
Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms. PAAP (2011)
Amit Kumar Singh, Wu Jigang, Akash Kumar, Thambipillai Srikanthan
Run-time mapping of multiple communicating tasks on MPSoC platforms. ICCS (1) (2010)
Wu Jigang, Thambipillai Srikanthan, Guang Chen
Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms. IEEE Trans. Computers 59 (4) (2010)
Abhijit Ray, Thambipillai Srikanthan, Wu Jigang
Rapid Techniques for Performance Estimation of Processors. J. Res. Pract. Inf. Technol. 42 (2) (2010)
Baofang Chang, Wu Jigang, Thambipillai Srikanthan, Lian Li
A Novel Approach for Multilevel Fixed Outline Floorplanning. PAAP (2010)
Jing Wang, Wu Jigang, Yuanrui Zhang, Dakun Zhang
Accelerating Reconfiguration for Degradable Mesh-Connected Processor Arrays. PAAP (2010)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Selecting profitable custom instructions for reconfigurable processors. J. Syst. Archit. 56 (8) (2010)
Amit Kumar Singh, Thambipillai Srikanthan, Akash Kumar, Wu Jigang
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. J. Syst. Archit. 56 (7) (2010)
Wu Jigang, Ting Lei, Thambipillai Srikanthan
Efficient Approximate Algorithm for Hardware/Software Partitioning. ACIS-ICIS (2009)
Wu Jigang, Baofang Chang, Thambipillai Srikanthan
A Hybrid Branch-and-Bound Strategy for Hardware/Software Partitioning. ACIS-ICIS (2009)
Amit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan
Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms. DSD (2009)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection. ACIS-ICIS (2009)
Tao Li, Zhigang Sun, Wu Jigang, Xicheng Lu
Fast enumeration of maximal valid subgraphs for custom-instruction identification. CASES (2009)
Amit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan
Efficient Heuristics for Minimizing Communication Overhead in NoC-based Heterogeneous MPSoC Platforms. IEEE International Workshop on Rapid System Prototyping (2009)
Siew Kei Lam, Huang Fan, Thambipillai Srikanthan, Wu Jigang
Run-time management of custom instructions on a partially reconfigurable architecture. Int. J. Inf. Commun. Technol. 2 (1/2) (2009)
Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan
A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. SPAA (2008)
Wu Jigang, Thambipillai Srikanthan, Kai Wang
Finding minimum interconnect sub-arrays in reconfigurable VLSI arrays. ISCAS (2008)
Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
Performance Estimation: IPC. ICYCS (2008)
Wu Jigang, Thambipillai Srikanthan, Tao Jiao
Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design. Des. Autom. Embed. Syst. 12 (4) (2008)
Wu Jigang, Thambipillai Srikanthan, Guang Chen
One-dimensional Search Algorithms for Hardware/Software Partitioning. MEMOCODE (2007)
Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan
Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors. ASAP (2007)
Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. IEEE Trans. Computers 56 (10) (2007)
Wu Jigang, Thambipillai Srikanthan
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches. IEEE Trans. Computers 55 (3) (2006)
Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang
New Reconfiguration Algorithm for Degradable VLSI Arrays. APCCAS (2006)
Wu Jigang, Thambipillai Srikanthan
Algorithmic aspects of area-efficient hardware/software partitioning. J. Supercomput. 38 (3) (2006)
Wu Jigang, Thambipillai Srikanthan
Low-complex dynamic programming algorithm for hardware/software partitioning. Inf. Process. Lett. 98 (2) (2006)
Leipo Yan, Siew Kei Lam, Thambipillai Srikanthan, Wu Jigang
Energy Efficient Cache Tuning with Performance Bound. DELTA (2006)
Wu Jigang, Thambipillai Srikanthan
An efficient algorithm for the collapsing knapsack problem. Inf. Sci. 176 (12) (2006)
Wu Jigang, Thambipillai Srikanthan, Tao Jiao
Efficient algorithm for functional scheduling in hardware/software co-design. FPT (2006)
Wu Jigang, Thambipillai Srikanthan
Efficient Algorithms for Hardware/Software Partitioning to Minimize Hardware Area. APCCAS (2006)
Wu Jigang, Thambipillai Srikanthan, Chengbin Yan
Minimizing Power in Hardware/Software Partitioning. Asia-Pacific Computer Systems Architecture Conference (2005)
Wu Jigang, Thambipillai Srikanthan, Heiko Schröder
Efficient reconfigurable techniques for VLSI arrays with 6-port switches. IEEE Trans. Very Large Scale Integr. Syst. 13 (8) (2005)
Wu Jigang, Thambipillai Srikanthan
Power Efficient Sub-Array in Reconfigurable VLSI Meshes. J. Comput. Sci. Technol. 20 (5) (2005)
Abhijit Ray, Thambipillai Srikanthan, Wu Jigang
Practical Techniques for Performance Estimation of Processors. IWSOC (2005)
Wu Jigang, Thambipillai Srikanthan, Heiko Schröder
Efficient Techniques and Hardware Analysis for Mesh-Connected Processors. ICA3PP (2005)
Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
Knapsack Model and Algorithm for HW/SW Partitioning Problem. International Conference on Computational Science (2004)
Wu Jigang, Thambipillai Srikanthan
An efficient data structure for branch-and-bound algorithm. Inf. Sci. 167 (1-4) (2004)
Wu Jigang, Thambipillai Srikanthan
Finding High Performance Solution in Reconfigurable Mesh-Connected VLSI Arrays. Asia-Pacific Computer Systems Architecture Conference (2004)
Wu Jigang, Thambipillai Srikanthan
Fast reconfiguring mesh-connected VLSI arrays. ISCAS (2) (2004)
Abhijit Ray, Wu Jigang, Thambipillai Srikanthan
Knapsack Model and Algorithm for Hardware/Software Partitioning Problem. Comput. Artif. Intell. 23 (5) (2004)
Wu Jigang, Thambipillai Srikanthan
A Run-time Reconfiguration Algorithm for VLSI Arrays. VLSI Design (2003)
Wu Jigang, Thambipillai Srikanthan
An improved reconfiguration algorithm for degradable VLSI/WSI arrays. J. Syst. Archit. 49 (1-2) (2003)
Wu Jigang, Thambipillai Srikanthan
On the Reconfiguration Algorithm for Fault-Tolerant VLSI Arrays. International Conference on Computational Science (2003)
Wu Jigang, Thambipillai Srikanthan, Chandni R. Patel
A Low Power Algorithm for Reconfigurable VLSI/WSI Arrays. Embedded Systems and Applications (2003)
Wu Jigang, Thambipillai Srikanthan
Partial rerouting algorithm for reconfigurable VLSI arrays. ISCAS (5) (2003)
Wu Jigang, Heiko Schröder, Thambipillai Srikanthan
New Architecture and Algorithms for Degradable VLSI/WSI Arrays. COCOON (2002)
Wu Jigang, Lei Yunfei, Heiko Schröder
A Minimal Reduction Approach for the Collapsing Knapsack Problem. Comput. Artif. Intell. 20 (4) (2001)
Wu Jigang, Yongchang Ji, Guoliang Chen
An Optimal Online Algorithm for Halfplane Intersection. J. Comput. Sci. Technol. 15 (3) (2000)