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Power Efficient Sub-Array in Reconfigurable VLSI Meshes.
Wu Jigang
Thambipillai Srikanthan
Published in:
J. Comput. Sci. Technol. (2005)
Keyphrases
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low cost
efficient implementation
signal processing
power consumption
vlsi design
database
neural network
search engine
general purpose
computationally efficient
systolic array