Tao Li

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 11

Top Topics

Future Directions

Level Parallelism

Packet Forwarding

Dedicated Hardware

Top Venues

Publications

Zilin Shi, Hui Yang, Junnan Li, Chenglong Li, Tao Li, Baosheng Wang
MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables. IEEE Access 8 (2020)
Chenglong Li, Tao Li, Junnan Li, Zilin Shi, Baosheng Wang
Update Latency Optimization of Packet Classification for SDN Switch on FPGA. FCCM (2020)
Junnan Li, Biao Han, Zhigang Sun, Tao Li, Xiaoyan Wang
Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches. IEICE Trans. Commun. (9) (2019)
Jinshu Su, Biao Han, Gaofeng Lv, Tao Li, Zhigang Sun
A Heterogeneous Parallel Packet Processing Architecture for NFV Acceleration. ICNP (2019)
Xiangrui Yang, Zhigang Sun, Junnan Li, Jinli Yan, Tao Li, Wei Quan, Donglai Xu, Gianni Antichi
FAST: enabling fast software/hardware prototype for network experimentation. IWQoS (2019)
Wenwen Fu, Tao Li, Jialun Yang, Junnan Li, Zhigang Sun
STRIDE: Single-Trip-Time Based Reliable Data Transport Protocol for the Reconfigurable Cloud. ICC (2019)
Chenglong Li, Tao Li, Junnan Li, Hui Yang, Baosheng Wang
A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement). SPAA (2019)
Wenwen Fu, Tao Li, Zhigang Sun
FAS: Using FPGA to Accelerate and Secure SDN Software Switches. Secur. Commun. Networks 2018 (2018)
Jinli Yan, Tao Li, Sheng Wang, Gaofeng Lv, Zhigang Sun
Demonstration of Path-Based Packet Batcher for Accelerating Vectorized Packet Processing. SECON (2018)
Jinli Yan, Lu Tang, Zhigang Sun, Tao Li, Donglai Xu
Self-described buffer: A novel mechanism to improve packet I/O efficiency in Linux. IWQoS (2016)
Tao Zhao, Tao Li, Biao Han, Zhigang Sun, Jinfeng Huang
Design and implementation of Software Defined Hardware Counters for SDN. Comput. Networks 102 (2016)
Lu Tang, Jinli Yan, Zhigang Sun, Tao Li, Minxuan Zhang
Towards high-performance packet processing on commodity multi-cores: current issues and future directions. Sci. China Inf. Sci. 58 (12) (2015)
Lu Tang, Zhigang Sun, Tao Li, Biao Han, Gaofeng Lv, Wei Shi, Hui Yang
Demostration of Self-Described Buffer for Accelerating Packet Forwarding on Multi-core Servers. CloudCom (2014)
Tao Zhao, Tao Li, Biao Han, Zhigang Sun, Jinfeng Huang
The Demonstration of Hyper Software Defined Hardware Counters. CloudCom (2014)
Tao Zhao, Tao Li, Biao Han, Zhigang Sun, Jinfeng Huang
Design of Software Defined hardware counters for SDN. LANMAN (2014)
Gaofeng Lv, Zhigang Sun, Yijiao Chen, Tao Li
Towards Internet Innovation: Software Defined Data Plane. ICoC (2013)
Hongyi Chen, Zhigang Sun, Bin Huang, Tao Li, Xilong Mao
Who is more reliable?: an evaluation method for distributed-memory aggregation in the internet. StudentWorkshop@CoNEXT (2012)
Hui Wang, Jianbiao Mao, Tao Li, Zhigang Sun, Zhenghu Gong, Gaofeng Lv
Neighbor Gradient-based Multicast Routing for Service-Oriented Applications. KSII Trans. Internet Inf. Syst. 6 (9) (2012)
Hui Wang, Jianbiao Mao, Zhigang Sun, Tao Li, Zhenghu Gong
Does one size fit all?: the impact of policy on multicast mechanism for future network. StudentWorkshop@CoNEXT (2011)
Tao Li, Zhigang Sun, Chunbo Jia, Qi Su, Myungjin Lee
Using NetMagic to observe fine-grained per-flow latency measurements. SIGCOMM (2011)
Tao Li, Jigang Wu, Yun Deng, Thambipillai Srikanthan, Xicheng Lu
Accelerating identification of custom instructions for extensible processors. IET Circuits Devices Syst. 5 (1) (2011)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Selecting profitable custom instructions for reconfigurable processors. J. Syst. Archit. 56 (8) (2010)
Tao Li, Wu Jigang, Siew Kei Lam, Thambipillai Srikanthan, Xicheng Lu
Efficient Heuristic Algorithm for Rapid Custom-Instruction Selection. ACIS-ICIS (2009)
Tao Li, Zhigang Sun, Wu Jigang, Xicheng Lu
Fast enumeration of maximal valid subgraphs for custom-instruction identification. CASES (2009)
Tao Li, Xiaoming Zhang, Zhigang Sun
DynaNP - A Coarse-grain Dataflow Network Processor Architecture with Dynamic Configurable Processing Path. SNPD (3) (2007)