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Trans. High Perform. Embed. Archit. Compil.
2007
2011
2015
2019
2007
2019
Keyphrases
Publications
volume 5, 2019
Tjerk Bijlsma
,
Marco Jan Gerrit Bekooij
,
Gerard J. M. Smit
Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
Carlos S. de La Lama
,
Pekka Jääskeläinen
,
Heikki Kultala
,
Jarmo Takala
Programmable and Scalable Architecture for Graphics Processing Units.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
Andreas Genser
,
Christian Bachmann
,
Christian Steger
,
Reinhold Weiss
,
Josef Haid
A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
George Kalokerinos
,
Vassilis Papaefstathiou
,
George Nikiforos
,
Stamatis G. Kavadias
,
Xiaojun Yang
,
Dionisios N. Pnevmatikatos
,
Manolis Katevenis
Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
Ricardo S. Ferreira
,
Cristoferson Bueno
,
Marcone Laure
,
Monica Magalhães Pereira
,
Luigi Carro
A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
Paul M. Carpenter
,
Alex Ramírez
,
Eduard Ayguadé
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
Richard Membarth
,
Hritam Dutta
,
Frank Hannig
,
Jürgen Teich
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards.
Trans. High Perform. Embed. Archit. Compil.
5 (2019)
volume 4, 2011
Frederik Vandeputte
,
Lieven Eeckhout
Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Nan Yuan
,
Lei Yu
,
Dongrui Fan
An Efficient and Flexible Task Management for Many Cores.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Frederik Vandeputte
,
Lieven Eeckhout
Finding Extreme Behaviors in Microprocessor Workloads.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
William Plishker
,
Nimish Sane
,
Mary Kiemb
,
Shuvra S. Bhattacharyya
Heterogeneous Design in Functional DIF.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Nan Wu
,
Qianming Yang
,
Mei Wen
,
Yi He
,
Ju Ren
,
Maolin Guan
,
Chunyuan Zhang
Tiled Multi-Core Stream Architecture.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Michael B. Henry
,
Leyla Nazhandali
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Omer Khan
,
Sandip Kundu
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Xiongfei Liao
,
Wu Jigang
,
Thambipillai Srikanthan
A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Markus Rullmann
,
Renate Merker
A Cost Model for Partial Dynamic Reconfiguration.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Timothy M. Jones
,
Michael F. P. O'Boyle
,
Jaume Abella
,
Antonio González
Compiler Directed Issue Queue Energy Reduction.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Yasutaka Wada
,
Akihiro Hayashi
,
Takeshi Masuura
,
Jun Shirako
,
Hirofumi Nakano
,
Hiroaki Shikano
,
Keiji Kimura
,
Hironori Kasahara
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Magnus Jahre
,
Lasse Natvig
A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Valeriu Beiu
,
Basheer A. M. Madappuram
,
Peter M. Kelly
,
Liam McDaid
On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Sai Prashanth Muralidhara
,
Mahmut T. Kandemir
Communication Based Proactive Link Power Management.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Daniel Llorente
,
Kimon Karras
,
Thomas Wild
,
Andreas Herkersdorf
Advanced Packet Segmentation and Buffering Algorithms in Network Processors.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Stanley Jaddoe
,
Mark Thompson
,
Andy D. Pimentel
Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Ben Cope
,
Peter Y. K. Cheung
,
Wayne Luk
,
Lee W. Howes
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Mohammad Ansari
,
Mikel Luján
,
Christos Kotselidis
,
Kim Jarvis
,
Chris C. Kirkham
,
Ian Watson
Transaction Reordering to Reduce Aborts in Software Transactional Memory.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Arnaldo Azevedo
,
Ben H. H. Juurlink
,
Cor Meenderinck
,
Andrei Sergeevich Terechko
,
Jan Hoogerbrugge
,
Mauricio Alvarez
,
Alex Ramírez
,
Mateo Valero
A Highly Scalable Parallel Implementation of H.264.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
Adam Welc
,
Bratin Saha
Software Transactional Memory Validation - Time and Space Considerations.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
William George Osborne
,
Wayne Luk
,
José Gabriel F. Coutinho
,
Oskar Mencer
Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.
Trans. High Perform. Embed. Archit. Compil.
4 (2011)
volume 3, 2011
Miquel Moretó
,
Francisco J. Cazorla
,
Alex Ramírez
,
Mateo Valero
Dynamic Cache Partitioning Based on the MLP of Cache Misses.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Tobias Klug
,
Michael Ott
,
Josef Weidendorfer
,
Carsten Trinitis
autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Chun-Chieh Lin
,
Chuen-Liang Chen
Cache Sensitive Code Arrangement for Virtual Machine.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Isao Kotera
,
Kenta Abe
,
Ryusuke Egawa
,
Hiroyuki Takizawa
,
Hiroaki Kobayashi
Power-Aware Dynamic Cache Partitioning for CMPs.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Fernando Latorre
,
Grigorios Magklis
,
José González
,
Pedro Chaparro
,
Antonio González
CROB: Implementing a Large Instruction Window through Compression.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Sandro Bartolini
,
Pierfrancesco Foglia
,
Cosimo Antonio Prete
Eighth MEDEA Workshop.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Tarik Saidani
,
Lionel Lacassagne
,
Joel Falcou
,
Claude Tadonki
,
Samir Bouaziz
Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Harald Devos
,
Jan Van Campenhout
,
Ingrid Verbauwhede
,
Dirk Stroobandt
Constructing Application-Specific Memory Hierarchies on FPGAs.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Matthias A. Blumrich
,
Valentina Salapura
,
Alan Gara
Exploring the Architecture of a Stream Register-Based Snoop Filter.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Yiannakis Sazeides
,
Andreas Moustakas
,
Kypros Constantinides
,
Marios Kleanthous
Improving Branch Prediction by Considering Affectors and Affectees Correlations.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Jan Hoogerbrugge
,
Andrei Sergeevich Terechko
A Multithreaded Multicore System for Embedded Media Processing.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
M. M. Waliullah
Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Subhradyuti Sarkar
,
Dean M. Tullsen
Data Layout for Cache Performance on a Multithreaded Architecture.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Maziar Goudarzi
,
Tohru Ishihara
,
Hamid Noori
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)
Mohammad Ansari
,
Mikel Luján
,
Christos Kotselidis
,
Kim Jarvis
,
Chris C. Kirkham
,
Ian Watson
Robust Adaptation to Available Parallelism in Transactional Memory Applications.
Trans. High Perform. Embed. Archit. Compil.
3 (2011)