Hiroaki Shikano

Publication Activity (10 Years)

Years Active: 2003-2017
Publications (10 Years): 1

Top Topics

Collaborative Systems

Addressing These Issues

Enabling Technology

Top Venues

Publications

Hiroaki Shikano, Takeshi Shibata, Qifeng Shen, Miyuki Hanaoka, Mariko Miyaki, Masahide Ban, Prasad Rallapalli, Yukinori Sakashita
QoS Analysis on Cable Video Delivery Networks. DCNET (2017)
Hiroaki Shikano, Machiko Asaie, Junji Yamamoto, Tatsuya Saito, Shunsuke Ota, Keitaro Uehara
Study on supporting technology for operational procedure design of IT systems in cloud-era datacenters. SAC (2013)
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Tadayoshi Enomoto, Suguru Nagayama, Hiroaki Shikano, Yousuke Hagiwara
Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. IEICE Trans. Electron. (4) (2008)
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Trans. Electron. (4) (2008)
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC (2008)
Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43 (4) (2008)
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Power-Aware Compiler Controllable Chip Multiprocessor. PACT (2007)
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Performance Evaluation of Compiler Controlled Power Saving Scheme. ISHPC (2005)
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Compiler Control Power Saving Scheme for Multi Core Processors. LCPC (2005)
Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. IEEE J. Solid State Circuits 38 (7) (2003)