Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array.
Tadayoshi EnomotoSuguru NagayamaHiroaki ShikanoYousuke HagiwaraPublished in: IEICE Trans. Electron. (2008)
Keyphrases
- low power
- high speed
- cmos technology
- power consumption
- single chip
- nm technology
- low power consumption
- vlsi architecture
- digital signal processing
- logic circuits
- mixed signal
- image sensor
- power dissipation
- low cost
- gate array
- power reduction
- wireless transmission
- frame rate
- ultra low power
- focal plane
- vlsi circuits
- high power
- low voltage
- analog to digital converter
- design considerations
- delay insensitive
- design process
- real time
- power saving
- power management
- hardware and software
- image processing