Power-Aware Compiler Controllable Chip Multiprocessor.
Hiroaki ShikanoJun ShirakoYasutaka WadaKeiji KimuraHironori KasaharaPublished in: IEICE Trans. Electron. (2008)
Keyphrases
- level parallelism
- multithreading
- ibm power processor
- high speed
- chip design
- programming language
- computational power
- power consumption
- instruction scheduling
- low cost
- high density
- general purpose
- database machines
- scheduling algorithm
- analog vlsi
- power distribution
- highly parallel
- distributed memory
- parallel computing
- instruction set
- software systems
- error resilience
- single chip
- memory subsystem