Yasutaka Wada

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 17

Top Topics

Neural Network Training

Pavement Distress

Top Venues

IEICE Trans. Electron.

Publications

Ryusuke Egawa, Yasutaka Wada
Special Issue on COOL Chips. IEEE Micro 44 (1) (2024)
Ryusuke Egawa, Yasutaka Wada
Foreword. IEICE Trans. Electron. 107 (6) (2024)
Ryusuke Egawa, Yasutaka Wada
Special Issue on Cool Chips. IEEE Micro 43 (1) (2023)
Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto
Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems. Int. J. Netw. Comput. 13 (1) (2023)
Ryusuke Egawa, Yasutaka Wada
Foreword. IEICE Trans. Electron. 106 (6) (2023)
Yoshiyuki Morie, Yasutaka Wada, Ryohei Kobayashi, Ryuichi Sakamoto
Performance Evaluation of Data Transfer API for Rank Level Approximate Computing on HPC Systems. IPDPS Workshops (2022)
Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Guanqin Pan, Thang Cao, Masaaki Kondo
Efficient and Precise Profiling, Modeling and Management on Power and Performance for Power Constrained HPC Systems. IEICE Trans. Electron. (6) (2021)
Yunjiao Ma, Yuan He, Yasutaka Wada, Wenchao Luo, Ryuichi Sakamoto, Masaaki Kondo
Mitigating Process Variations with Cooperative Tuning for Performance and Power through a Simple DSL. CANDAR (Workshops) (2021)
Hyuga Hashimoto, Ryo Naka, Yasutaka Wada
An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit". FPT (2021)
Jonas T. Agyepong, Mostafa Soliman, Yasutaka Wada, Keiji Kimura, Ahmed El-Mahdy
Secure Image Inference Using Pairwise Activation Functions. IEEE Access 9 (2021)
Musashi Aoto, Moe Mitsugi, Takumi Momose, Yasutaka Wada
Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training. FPT (2019)
Musashi Aoto, Yasutaka Wada, Yousuke Numata
Development of an FPGA Controlled "Mini-Car" Toward Autonomous Driving. FPT (2018)
Yasutaka Wada, Yuan He, Thang Cao, Masaaki Kondo
A Power Management Framework with Simple DSL for Automatic Power-Performance Optimization on Power-Constrained HPC Systems. SCFA (2018)
Mamoru Shimaoka, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers. LCPC (2015)
Ghada Y. Abozaid, Arnaud Tisserand, Ahmed El-Mahdy, Yasutaka Wada
Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier. IEEE Embed. Syst. Lett. 7 (3) (2015)
Yuichi Inadomi, Tapasya Patki, Koji Inoue, Mutsumi Aoyagi, Barry Rountree, Martin Schulz, David K. Lowenthal, Yasutaka Wada, Keiichiro Fukazawa, Masatsugu Ueda, Masaaki Kondo, Ikuo Miyoshi
Analyzing and mitigating the impact of manufacturing variability in power-constrained supercomputing. SC (2015)
Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada
A Linear Time and Space Algorithm for Optimal Traffic-Signal Duration at an Intersection. IEEE Trans. Intell. Transp. Syst. 16 (1) (2015)
Ghada Y. Abozaid, Ahmed El-Mahdy, Yasutaka Wada
A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption. DSD (2013)
Sameh Samra, Ahmed El-Mahdy, Yasutaka Wada
A Linear-Time and Space Algorithm for Optimal Traffic Signal Durations at an Intersection. CoRR (2013)
Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. Trans. High Perform. Embed. Archit. Compil. 4 (2011)
Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. (4) (2011)
Sameh Samra, Ahmed El-Mahdy, Walid Gomaa, Yasutaka Wada, Amin A. Shoukry
Efficient Parallel Implementations of Controlled Optimization of Traffic Phases. ICA3PP (1) (2011)
Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC (2010)
Akihiro Hayashi, Yasutaka Wada, Takeshi Watanabe, Takeshi Sekiguchi, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara
Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. LCPC (2010)
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Power-Aware Compiler Controllable Chip Multiprocessor. IEICE Trans. Electron. (4) (2008)
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, Masayoshi Mase, Yasutaka Wada, Hirofumi Nakano, Keiji Kimura, Hironori Kasahara
Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. ISPA (2008)
Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Software-cooperative power-efficient heterogeneous multi-core for media processing. ASP-DAC (2008)
Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. IEEE J. Solid State Circuits 43 (4) (2008)
Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
Power-Aware Compiler Controllable Chip Multiprocessor. PACT (2007)
Keiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara
Multigrain parallel processing on compiler cooperative chip multiprocessor. Interaction between Compilers and Computer Architectures (2005)
Jun Shirako, Munehiro Yoshida, Naoto Oshiyama, Yasutaka Wada, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Performance Evaluation of Compiler Controlled Power Saving Scheme. ISHPC (2005)
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara
Compiler Control Power Saving Scheme for Multi Core Processors. LCPC (2005)