Power-Aware Compiler Controllable Chip Multiprocessor.
Hiroaki ShikanoJun ShirakoYasutaka WadaKeiji KimuraHironori KasaharaPublished in: PACT (2007)
Keyphrases
- level parallelism
- multithreading
- ibm power processor
- power consumption
- high speed
- floating point unit
- power dissipation
- general purpose
- chip design
- low cost
- computational power
- analog vlsi
- instruction set
- instruction scheduling
- high density
- highly efficient
- real time
- highly optimized
- programmable logic
- multiprocessor systems
- highly parallel
- floating point
- parallel computing
- programming language