Frank Hannig

ORCID

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 81

Top Venues

CoRR

ASAP

J. Signal Process. Syst.

SCOPES

University of Erlangen-Nuremberg (PHD)

Education History

University of Erlangen-Nuremberg

PHD

Publications

Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS (2024)
Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR (2024)
Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich
Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE (2024)
Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS (2024)
Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR (2024)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC (2024)
Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig
Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. 52 (1-2) (2024)
Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR (2023)
Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen
Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys (2023)
Patrick Plagwitz, Frank Hannig, Jürgen Teich
TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL (2022)
Muhammad Sabih, Frank Hannig, Jürgen Teich
DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys (2022)
Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich
Hardware-Aware Evolutionary Filter Pruning. SAMOS (2022)
Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. 34 (14) (2022)
Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs 69 (6) (2022)
Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich
MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC (2022)
Frank Hannig, Steven Derrien
Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. 94 (9) (2022)
Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33 (14) (2021)
Frank Hannig, Dirk Koch
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 93 (12) (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. 20 (5) (2021)
Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich
Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL (2021)
Stefan Groth, Jürgen Teich, Frank Hannig
Efficient Application of Tensor Core Units for Convolving Images. SCOPES (2021)
Frank Hannig, Jürgen Teich
Open Source Hardware. Computer 54 (10) (2021)
Bo Qiao, Jürgen Teich, Frank Hannig
An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops (2021)
M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. 18 (3) (2021)
Muhammad Sabih, Frank Hannig, Jürgen Teich
Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops (2021)
Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR (2021)
Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich
A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM (2021)
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR (2021)
T. K. R. Arvind, Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT (2020)
Dirk Koch, Frank Hannig, Javier Navaridas
Message from the Conference Chairs - ASAP 2020. ASAP (2020)
Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC (2020)
Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops (2020)
Muhammad Sabih, Frank Hannig, Jürgen Teich
Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR (2020)
Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich
A bibliometric approach for detecting the gender gap in computer science. Commun. ACM 63 (5) (2020)
Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig
Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP (2020)
M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR (2020)
Christian Heidorn, Frank Hannig, Jürgen Teich
Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES (2020)
Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig
Efficient parallel reduction on GPUs with Hipacc. SCOPES (2020)
Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig
A runtime system for finite element methods in a partitioned global address space. CF (2020)
M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (11) (2020)
M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR (2020)
Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig
SYCL Code Generation for Multigrid Methods. SCOPES (2019)
Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO (2019)
Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich
Anytime instructions for programmable accuracy floating-point arithmetic. CF (2019)
Jörg Fickenscher, Frank Hannig, Jürgen Teich
DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS (2019)
Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. 14 (8) (2019)
Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. 5 (2019)
Michael Witterauf, Frank Hannig, Jürgen Teich
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE (2019)
Dietmar Fey, Frank Hannig
Special issue on heterogeneous real-time image processing. J. Real Time Image Process. 14 (3) (2018)
Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid
Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. 90 (1) (2018)
Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig
Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. 28 (4) (2018)
Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
Automatic Kernel Fusion for Image Processing DSLs. SCOPES (2018)
Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP (2018)
Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE (2018)
Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. FCCM (2018)
Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP (2018)
Christian Schmitt, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer
Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE 106 (11) (2018)
Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS (2018)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig (2017)
Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer
A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. 14 (2) (2017)
Didem Unat, Anshu Dubey, Torsten Hoefler, John Shalf, Mark James Abraham, Mauro Bianco, Bradford L. Chamberlain, Romain Cledat, H. Carter Edwards, Hal Finkel, Karl Fuerlinger, Frank Hannig, Emmanuel Jeannot, Amir Kamil, Jeff Keasler, Paul H. J. Kelly, Vitus J. Leung, Hatem Ltaief, Naoya Maruyama, Chris J. Newburn, Miquel Pericàs
Trends in Data Locality Abstractions for HPC Systems. IEEE Trans. Parallel Distributed Syst. 28 (10) (2017)
Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD (2017)
Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC (2017)
Michael Witterauf, Frank Hannig, Jürgen Teich
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP (2017)
Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal
A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. 89 (2) (2017)
Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66 (3) (2017)
Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig (2017)
Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich
Auto-vectorization for image processing DSLs. LCTES (2017)
Frank Hannig, João M. P. Cardoso, Dietmar Fey
Introduction to the special issue on architecture of computing systems. J. Syst. Archit. 77 (2017)
Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium (2017)
Sascha Roloff, Frank Hannig, Jürgen Teich
High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia (2017)
M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP (2017)
Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
Efficiency in ILP processing by using orthogonality. ASAP (2017)
Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP (2016)
Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS (2016)
Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58 (6) (2016)
Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
: A Domain-Specific Language and Compiler for Image Processing. IEEE Trans. Parallel Distributed Syst. 27 (1) (2016)
M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
FPGA-based accelerator design from a domain-specific language. FPL (2016)
Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich
ActorX10: an actor library for X10. X10@PLDI (2016)
Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich
Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT (2016)
Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES (2015)
Frank Hannig, Andreas Herkersdorf
Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. J. Syst. Archit. 61 (10) (2015)
Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey
Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. 61 (10) (2015)
Éricles Sousa, Frank Hannig, Jürgen Teich
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP (2015)
Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich
Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC (2015)
Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich
Loop coarsening in C-based High-Level Synthesis. ASAP (2015)
Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61 (10) (2015)
Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich
Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia (2015)
Frank Hannig, Dirk Koch, Daniel Ziener
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR (2015)
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE (2015)
Frank Hannig, Dietmar Fey, Anton Lokhmotov
Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015). CoRR (2015)
Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey
Automatic Optimization of Hardware Accelerators for Image Processing. CoRR (2015)
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE (2014)
Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal
Domain-specific augmentations for High-Level Synthesis. ASAP (2014)
Christian Schmitt, Sebastian Kuckuk, Harald Köstler, Frank Hannig, Jürgen Teich
An Evaluation of Domain-Specific Language Technologies for Code Generation. ICCSA (Workshops/Short Papers/Posters) (2014)
Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
Massively Parallel Processor Architectures for Resource-aware Computing. CoRR (2014)
Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD (2014)

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Publication Activity (10 Years)

Top Topics

Top Venues

Frank Hannig