Dietmar Fey

ORCID

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 95

Top Venues

University of Erlangen-Nuremberg, Germany (PHD)

Education History

University of Erlangen-Nuremberg, Germany

PHD

Publications

Johannes Kliemt, Markus Fritscher, Dietmar Fey
Comparison of a Binary Signed-Digit Adder with Conventional Binary Adder Circuits on Layout Level. ARCS (2024)
Farhad Ebrahimi-Azandaryani, Dietmar Fey
ExTern: Boosting RISC-V core performance using ternary encoding. Microprocess. Microsystems 107 (2024)
Shima Hosseinzadeh, Marius Klemm, Georg Fischer, Dietmar Fey
Optimizing multi-level ReRAM memory for low latency and low energy consumption. it Inf. Technol. 65 (1-2) (2023)
Shima Hosseinzadeh, Amirhossein Parvaresh, Dietmar Fey
Optimization of OLAP In-Memory Database Management Systems with Processing-In-Memory Architecture. ARCS (2023)
Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures. IEEE Comput. Archit. Lett. 22 (1) (2023)
John Reuben, Dietmar Fey, Stefan Slesazeck
A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories. MOCAST (2023)
Dietmar Fey
Memristive computing in Germany. it Inf. Technol. 65 (1-2) (2023)
Stefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions. NANOARCH (2023)
Johannes Kliemt, Dietmar Fey
Work in Progress: Extending Virtual Prototypes of Microprocessor Architectures with Accuracy Tracing. SIMULTECH (2023)
Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Dietmar Fey
DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs. EDGE (2023)
Amirhossein Parvaresh, Shima Hosseinzadeh, Dietmar Fey
Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware Study. NANOARCH (2023)
Lars Schwenger, Philipp Holzinger, Dietmar Fey, Hector Gerardo Muñoz Hernandez, Marc Reichenbach
EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis. SAMOS (2022)
Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer
Closing the Performance Gap with Modern C++. CoRR (2022)
Farehe Giahi, Sebastian Rachuj, Dietmar Fey
Investigating SAMV Regarding its Suitability For FPGAs. SOCC (2022)
Johannes Lex, Ulrich Margull, Dietmar Fey, Ralph Mader
Fault Tolerance in Heterogeneous Automotive Real-time Systems. Echtzeit (2021)
Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey
RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. IEEE Access 9 (2021)
Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS (2021)
Dietmar Fey, John Reuben, Stefan Slesazeck
Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic. ICECS (2021)
John Reuben, Dietmar Fey
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. ISVLSI (2021)
Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Marc Reichenbach, Dietmar Fey
A Case for Function-as-a-Service with Disaggregated FPGAs. CLOUD (2021)
Anne D. Koelewijn, Musa L. Audu, Antonio J. del Ama, Annalisa Colucci, Josep M. Font-Llagunes, Antonio Gogeascoechea, Sandra K. Hnat, Nathan Makowski, Juan C. Moreno, Mark J. Nandor, Roger D. Quinn, Marc Reichenbach, Ryan-David Reyes, Massimo Sartori, Surjo R. Soekadar, Ronald J. Triolo, Mareike Vermehren, Christian Wenger, Utku S. Yavuz, Dietmar Fey, Philipp Beckerle
Adaptation Strategies for Personalized Gait Neuroprosthetics. Frontiers Neurorobotics 15 (2021)
Steffen Vaas, Peter Ulbrich, Christian Eichler, Peter Wägemann, Marc Reichenbach, Dietmar Fey
Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. ISORC (2021)
Dietmar Fey, John Reuben
Direct state transfer in MLC based memristive ReRAM devices for ternary computing. ECCTD (2020)
Shima Hosseinzadeh, Mehrdad Biglari, Dietmar Fey
TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities. DSD (2020)
Dietmar Fey, Wolfgang Karl, Theo Ungerer
Memristoren für zukünftige Rechnersysteme. Inform. Spektrum 43 (1) (2020)
Herbert Jordan, Philipp Gschwandtner, Peter Thoman, Peter Zangerl, Alexander Hirsch, Thomas Fahringer, Thomas Heller, Dietmar Fey
The allscale framework architecture. Parallel Comput. 99 (2020)
Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation. H2RC@SC (2020)
Sebastian Rachuj, Dietmar Fey, Marc Reichenbach
Impact of Performance Estimation on Fast Processor Simulators. SimuTools (2) (2020)
Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. Supercomput. Front. Innov. 7 (2) (2020)
Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, Marc Reichenbach
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. MOCAST (2020)
Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters. FCCM (2020)
John Reuben, Dietmar Fey
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM. NORCAS (2019)
Tobias Lieske, Wilfried Uhring, Norbert Dumas, Anastasia Ioanna Skilitski, Jérémie Léonard, Dietmar Fey
Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications. J. Signal Process. Syst. 91 (7) (2019)
Rashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey
A Hardware Inference Accelerator for Temporal Convolutional Networks. NORCAS (2019)
Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. J. Signal Process. Syst. 91 (7) (2019)
Johannes Hofmann, Christie L. Alappat, Georg Hager, Dietmar Fey, Gerhard Wellein
Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors. CoRR (2019)
Alexander Ditter, Michael Tielemann, Dietmar Fey
Bridging the Gap between High-Performance, Cloud and Service-Oriented Computing. FAS*W@SASO/ICAC (2019)
Burkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration. FPL (2019)
Markus Fritscher, Johannes Knödtel, Marc Reichenbach, Dietmar Fey
Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. ICECS (2019)
Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. J. Signal Process. Syst. 91 (7) (2019)
Sebastian Rachuj, Marc Reichenbach, Dietmar Fey
A Generic Functional Simulation of Heterogeneous Systems. ARCS (2019)
Dietmar Fey, Frank Hannig
Special issue on heterogeneous real-time image processing. J. Real Time Image Process. 14 (3) (2018)
Johannes Hofmann, Georg Hager, Dietmar Fey
On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. ISC (2018)
Wolfgang Bauer, Philipp Holzinger, Marc Reichenbach, Steffen Vaas, Paul Hartke, Dietmar Fey
Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. Euro-Par Workshops (2018)
Philipp Holzinger, Marc Reichenbach, Dietmar Fey
A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems. SAMOS (2018)
Christopher Soell, Marc Reichenbach, Juergen Roeber, Amelie Hagelauer, Robert Weigel, Dietmar Fey
Case study on memristor-based multilevel memories. Int. J. Circuit Theory Appl. 46 (1) (2018)
Herbert Jordan, Thomas Heller, Philipp Gschwandtner, Peter Zangerl, Peter Thoman, Dietmar Fey, Thomas Fahringer
The AllScale Runtime Application Model. CLUSTER (2018)
Anderson M. Maliszewski, Dalvan Griebler, Claudio Schepke, Alexander Ditter, Dietmar Fey, Luiz Gustavo Fernandes
The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM. HPCS (2018)
Mehrdad Biglari, Tobias Lieske, Dietmar Fey
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. NANOARCH (2018)
Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. PATMOS (2018)
Johannes Hofmann, Georg Hager, Dietmar Fey
On the accuracy and usefulness of analytic energy models for contemporary multicore processors. CoRR (2018)
Tobias Lieske, Mehrdad Biglari, Dietmar Fey
Multi-level memristive voltage divider: programming scheme trade-offs. MEMSYS (2018)
Sebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. ARCS (2018)
Marc Reichenbach, Lukas Liebischer, Steffen Vaas, Dietmar Fey
Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. DASIP (2018)
Sebastian Rachuj, Marc Reichenbach, Steffen Vaas, Dietmar Fey
Autonomous Driving in the Curriculum of Computer Architecture. EWME (2018)
Daniel Wust, Dietmar Fey, Johannes Knödtel
A programmable ternary CPU using hybrid CMOS/memristor circuits. Int. J. Parallel Emergent Distributed Syst. 33 (4) (2018)
Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing
Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Christian Hartmann, Dietmar Fey
An extended analysis of memory hierarchies for efficient implementations of image processing applications. J. Real Time Image Process. 14 (3) (2018)
Christian Hartmann, Konrad Häublein, Marc Reichenbach, Dietmar Fey
IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. J. Real Time Image Process. 14 (3) (2018)
Marc Reichenbach, Maximilian Kasparek, Konrad Häublein, Jan Niklas Bauer, Mohammad Alawieh, Dietmar Fey
Fast heterogeneous computing architectures for smart antennas. J. Syst. Archit. 76 (2017)
Tobias Lieske, Wilfried Uhring, Norbert Dumas, Jérémie Léonard, Dietmar Fey
Embedded fluorescence lifetime determination for high throughput real-time droplet sorting with microfluidics. DASIP (2017)
Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. DASIP (2017)
Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein
Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurr. Comput. Pract. Exp. 29 (9) (2017)
Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. DASIP (2017)
Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey
An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors. ISC (2017)
Dietmar Fey
Evaluating Ternary Adders using a hybrid Memristor / CMOS approach. CoRR (2017)
Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey
Prototyping memristors in digital system with an FPGA-based testing environment. PATMOS (2017)
Mehrdad Biglari, Dietmar Fey
Memristive voltage divider: a bipolar ReRAM-based unit for non-volatile flip-flops. MEMSYS (2017)
Alexander Ditter, Gabriel Graf, Dietmar Fey
Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure. CCB@EuroSys (2017)
Frank Hannig, João M. P. Cardoso, Dietmar Fey
Introduction to the special issue on architecture of computing systems. J. Syst. Archit. 77 (2017)
Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey
System on chip generation for multi-sensor and sensor fusion applications. SAMOS (2017)
Benjamin Pfundt, Marc Reichenbach, Dietmar Fey
Comprehensive curriculum for reconfigurable heterogeneous computer architecture education. IET Circuits Devices Syst. 11 (4) (2017)
Steffen Limmer, Dietmar Fey
Comparison of common parallel architectures for the execution of the island model and the global parallelization of evolutionary algorithms. Concurr. Comput. Pract. Exp. 29 (9) (2017)
Johannes Hofmann, Georg Hager, Gerhard Wellein, Dietmar Fey
An analysis of core- and chip-level architectural features in four generations of Intel server processors. CoRR (2017)
Hoang Anh Du Nguyen, Jintao Yu, Lei Xie, Mottaqiallah Taouil, Said Hamdioui, Dietmar Fey
Memristive devices for computing: Beyond CMOS and beyond von Neumann. VLSI-SoC (2017)
Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein
Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. ARCS (2016)
Benjamin Pfundt, Marc Reichenbach, Christian Hartmann, Konrad Häublein, Dietmar Fey
Teaching heterogeneous computer architectures using smart camera systems. EWME (2016)
Johannes Hofmann, Dietmar Fey
An ECM-based energy-efficiency optimization approach for bandwidth-limited streaming kernels on recent Intel Xeon processors. CoRR (2016)
Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS (2016)
Steffen Vaas, Marc Reichenbach, Dietmar Fey
An Application-Specific Instruction Set Processor for Power Quality Monitoring. IPDPS Workshops (2016)
Johannes Hofmann, Dietmar Fey
An ECM-based Energy-Efficiency Optimization Approach for Bandwidth-Limited Streaming Kernels on Recent Intel Xeon Processors. E2SC@SC (2016)
Konrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. ARC (2016)
Bruno Kleinert, Franziska Schäfer, Jupiter Bakakeu, Simone Weiß, Dietmar Fey
Hardware-software Co-simulation of Self-organizing Smart Home Networks - Who am I and Where Are the Others?. SIMULTECH (2016)
Dominik Schoenwetter, Alexander Ditter, Vadym Aizinger, Balthasar Reuter, Dietmar Fey
Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware. SIMULTECH (2016)
Bruno Kleinert, Simone Weiß, Franziska Schäfer, Jupiter Bakakeu, Dietmar Fey
Adaptive Synchronization Interface for Hardware-Software Co-Simulation based on SystemC and QEMU. SimuTools (2016)
Franz Richter-Gottfried, Patrick Kreutzer, Alexander Ditter, Max Schneider, Dietmar Fey
C++ Classes and Templates for OpenCL Kernels with PATOS. IWOCL (2016)
Dietmar Fey, Marc Reichenbach, Christopher Söll, Mehrdad Biglari, Jürgen Röber, Robert Weigel
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. MEMSYS (2016)
Steffen Limmer, Dietmar Fey
Investigation of strategies for an increasing population size in multi-objective CMA-ES. CEC (2016)
Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein
Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors. CoRR (2016)
Dominik Schoenwetter, Alexander Ditter, Dietmar Fey, Ralph Mader
Improving instruction accurate simulation for parallel automotive applications. SIES (2016)
Arne Hendricks, Thomas Heller, Andreas Schäfer, Maximilian Kasparek, Dietmar Fey
Evaluating Performance and Energy-Efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures. ICCS (2016)
Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey
The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. ReConFig (2016)
Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey
Dataflow optimization for programmable embedded image preprocessing accelerators. ReConFig (2016)
Thomas Heller, Hartmut Kaiser, Patrick Diehl, Dietmar Fey, Marc Alexander Schweitzer
Closing the Performance Gap with Modern C++. ISC Workshops (2016)
Arne Hendricks, Thomas Heller, Herbert Jordan, Peter Thoman, Thomas Fahringer, Dietmar Fey
The AllScale Runtime Interface - Theoretical Foundation and Concept. MTAGS@SC (2016)
Marc Reichenbach, Benjamin Pfundt, Dietmar Fey
Framework for parameter analysis of FPGA-based image processing architectures. SAMOS (2015)
Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein
Performance analysis of the Kahan-enhanced scalar product on current multicore processors. CoRR (2015)
Christian Herglotz, Jürgen Seiler, André Kaup, Arne Hendricks, Marc Reichenbach, Dietmar Fey
Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing. IPDPS Workshops (2015)
Johannes Hofmann, Jan Eitzinger, Dietmar Fey
Execution-Cache-Memory Performance Model: Introduction and Validation. CoRR (2015)
Christian Hartmann, Anna Yupatova, Marc Reichenbach, Dietmar Fey, Reinhard German
A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures. CoRR (2015)

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Publication Activity (10 Years)

Top Topics

Top Venues

Dietmar Fey