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John Reuben
ORCID
Publication Activity (10 Years)
Years Active: 2013-2023
Publications (10 Years): 12
Top Topics
Hash Table
Generation Algorithm
Low Power
Comparative Study
Top Venues
IEEE Trans. Circuits Syst. I Regul. Pap.
J. Circuits Syst. Comput.
ICECS
ASAP
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Publications
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John Reuben
,
Dietmar Fey
,
Stefan Slesazeck
A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories.
MOCAST
(2023)
Stefan Slesazeck
,
Suzanne Lancaster
,
John Reuben
,
Shima Hosseinzadeh
,
Dietmar Fey
,
Thomas Mikolajick
Hyper Dimensional Computing with Ferroelectric Tunneling Junctions.
NANOARCH
(2023)
Vijaya Lakshmi
,
Vikramkumar Pudi
,
John Reuben
Inner Product Computation In-Memory Using Distributed Arithmetic.
IEEE Trans. Circuits Syst. I Regul. Pap.
69 (11) (2022)
Vijaya Lakshmi
,
John Reuben
,
Vikramkumar Pudi
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
69 (3) (2022)
Dietmar Fey
,
John Reuben
,
Stefan Slesazeck
Comparative study of usefulness of FeFET, FTJ and ReRAM technology for ternary arithmetic.
ICECS
(2021)
John Reuben
,
Stefan Pechmann
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.
IEEE Trans. Very Large Scale Integr. Syst.
29 (6) (2021)
John Reuben
,
Dietmar Fey
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles.
ISVLSI
(2021)
Dietmar Fey
,
John Reuben
Direct state transfer in MLC based memristive ReRAM devices for ternary computing.
ECCTD
(2020)
John Reuben
,
Stefan Pechmann
A Parallel-friendly Majority Gate to Accelerate In-memory Computation.
ASAP
(2020)
John Reuben
,
Dietmar Fey
A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM.
NORCAS
(2019)
John Reuben
,
Rotem Ben Hur
,
Nimrod Wald
,
Nishil Talati
,
Ameer Haj Ali
,
Pierre-Emmanuel Gaillardon
,
Shahar Kvatinsky
Memristive logic: A framework for evaluation and comparison.
PATMOS
(2017)
Kamineni Sumanth Kumar
,
John Reuben
Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits.
J. Circuits Syst. Comput.
25 (11) (2016)
V. Mohammed Zackriya
,
John Reuben
,
Ashim Harsh
,
Harish M. Kittur
Low Power fractional-n frequency Divider with Improved Resolution.
J. Circuits Syst. Comput.
23 (8) (2014)
John Reuben
,
Harish M. Kittur
,
Mohd Shoaib
A novel clock generation algorithm for system-on-chip based on least common multiple.
Comput. Electr. Eng.
40 (7) (2014)
John Reuben
,
V. Mohammed Zackriya
,
Salma Nashit
,
Harish M. Kittur
Capacitance driven clock mesh synthesis to minimize skew and power dissipation.
IEICE Electron. Express
10 (24) (2013)