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Capacitance driven clock mesh synthesis to minimize skew and power dissipation.
John Reuben
V. Mohammed Zackriya
Salma Nashit
Harish M. Kittur
Published in:
IEICE Electron. Express (2013)
Keyphrases
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power dissipation
power consumption
low power
analog circuits
high speed
logic circuits
power reduction
power saving
cmos technology
digital signal processing
chip design
energy saving
clock gating
low cost
nm technology
neural network
design methodology
parallel algorithm
image registration
computer vision