Vikramkumar Pudi

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 26

Top Topics

Compressive Sensing

Field Programmable Gate Array

Pipelined Architecture

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Balasubramanyam Appina, Anupam Chattopadhyay
Image Compression Based on Near Lossless Predictive Measurement Coding for Block-Based Compressive Sensing. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
Redefining Clock Network Construction: The Nested Flex Paradigm for Enhanced PPA Dynamics. ISCAS (2024)
Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs. APCCAS (2023)
K. Lakshmi BhanuPrakash Reddy, Haripriya R. S, Keerthija Puli, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi
Design of Energy Efficient and Low Delay Posit Multiplier. VLSID (2023)
Lakshmi Sarvaani P, Subba Ramkumar Reddy Annapalli, Vikramkumar Pudi, Naga Teja Babu M
A Configurable Multi Source Clock Tree Synthesis For High Frequency Network On Chips. ISCAS (2023)
Keerthija Puli, Vikramkumar Pudi
Design of Low Power ALU for RISC-VISA. iSES (2023)
Vijaya Lakshmi, Vikramkumar Pudi, John Reuben
Inner Product Computation In-Memory Using Distributed Arithmetic. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Vijaya Lakshmi, John Reuben, Vikramkumar Pudi
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Ambati Sathvik, Tirunagari Rahul, Anubhab Baksi, Vikramkumar Pudi
Hardware Implementation of SpoC-128. IACR Cryptol. ePrint Arch. 2022 (2022)
K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. VDAT (2021)
K. B. Dheeraj Kumar, K. Lakshmi BhanuPrakash Reddy, Vikramkumar Pudi, Srinivasu Bodapati
Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs. iSES (2021)
Vikramkumar Pudi, Srinivasu Bodapati, Sachin Kumar, Anupam Chattopadhyay
Cyber Security Protocol for Secure Traffic Monitoring Systems using PUF-based Key Management. iSES (2020)
Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Duo Chen, Rosa Q. So, Anupam Chattopadhyay, Cuntai Guan
A Brain-Computer Interface Framework Based on Compressive Sensing and Deep Learning. IEEE Consumer Electron. Mag. 9 (3) (2020)
Tingting Zhang, Vikramkumar Pudi, Weiqiang Liu
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. ISQED (2019)
Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay
Lightweight ASIC Implementation of AEGIS-128. ISVLSI (2018)
Ritu Ranjan Shrivastwa, Vikramkumar Pudi, Anupam Chattopadhyay
An FPGA-Based Brain Computer Interfacing Using Compressive Sensing and Machine Learning. ISVLSI (2018)
Vishal Dey, Vikramkumar Pudi, Anupam Chattopadhyay, Yuval Elovici
Security Vulnerabilities of Unmanned Aerial Vehicles and Countermeasures: An Experimental Study. VLSI Design (2018)
B. Srinivasu, Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
CoLPUF : A Novel Configurable LFSR-based PUF. APCCAS (2018)
Ming Ming Wong, Vikramkumar Pudi, Anupam Chattopadhyay
Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. VLSI-SoC (2018)
Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
Secure and Lightweight Compressive Sensing Using Stream Cipher. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Vikramkumar Pudi, Anupam Chattopadhyay, Kwok-Yan Lam
Efficient and Lightweight Quantized Compressive Sensing using μ-Law. ISCAS (2018)
Debjyoti Bhattacharjee, Vikramkumar Pudi, Anupam Chattopadhyay
SHA-3 implementation using ReRAM based in-memory computing architecture. ISQED (2017)
Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. IEEE Trans. Computers 66 (10) (2017)
Vikramkumar Pudi, Anupam Chattopadhyay, Thambipillai Srikanthan
Modified projected Landweber method for Compressive-Sensing reconstruction of images with non-orthogonal matrices. ISIC (2016)
Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. ISVLSI (2016)
Vikramkumar Pudi, K. Sridharan
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Tahiyah Nou Shene, Vikramkumar Pudi, K. Sridharan, Vineetha Thomas, J. Arthi
Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle. IET Comput. Vis. 9 (4) (2015)