Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
Vikramkumar PudiK. SridharanFabrizio LombardiPublished in: IEEE Trans. Computers (2017)
Keyphrases
- logic circuits
- power dissipation
- flip flops
- nm technology
- low power
- delay insensitive
- power consumption
- digital circuits
- chip design
- computational complexity
- decision problems
- cmos technology
- high speed
- logic synthesis
- worst case
- space complexity
- parallel processing
- circuit design
- classical logic
- parallel implementation
- shared memory
- data flow
- optimization methods
- modal logic
- logic programming