Design of Low Area and Low Power Systolic Serial Parallel Multiplier using CNTFETs.
K. B. Dheeraj KumarK. Lakshmi BhanuPrakash ReddyVikramkumar PudiSrinivasu BodapatiPublished in: iSES (2021)
Keyphrases
- low power
- low power consumption
- low cost
- single chip
- power consumption
- high speed
- logic circuits
- vlsi architecture
- cmos technology
- digital signal processing
- gate array
- power dissipation
- power reduction
- computer architecture
- real time
- design process
- mixed signal
- vlsi circuits
- design considerations
- floating point
- power saving
- hardware implementation
- parallel processing
- high power
- signal processor
- image processing