Daniel Ziener

ORCID

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 20

Top Venues

University of Erlangen-Nuremberg (PHD)

Education History

University of Erlangen-Nuremberg

PHD

Publications

Ali Asghar, Amanda Katherine Robillard, Ilya Tuzov, Andreas Becher, Daniel Ziener
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs. ARCS (2022)
Hasan Irmak, Daniel Ziener, Nikolaos Alachiotis
Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. FPL (2021)
Hasan Irmak, Nikolaos Alachiotis, Daniel Ziener
An Energy-Efficient FPGA-based Convolutional Neural Network Implementation. SIU (2021)
Ali Asghar, Benjamin Hettwer, Emil Karimov, Daniel Ziener
Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. ARC (2021)
Pepijn de Vos, Michael Kirchhoff, Daniel Ziener
A Complete Open Source Design Flow for Gowin FPGAs. FPT (2020)
Ali Asghar, Rick van Loo, Timon Kruiper, Daniel Ziener
Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. FPT (2019)
Daniel Ziener, Jutta Pirkl, Jürgen Teich
Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig (2018)
Thorbjörn Posewsky, Daniel Ziener
Throughput Optimizations for FPGA-based Deep Neural Network Inference. CoRR (2018)
Thorbjörn Posewsky, Daniel Ziener
A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks. ARCS (2018)
Daniel Ziener
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems. CoRR (2018)
Thorbjörn Posewsky, Daniel Ziener
Throughput optimizations for FPGA-based deep neural network inference. Microprocess. Microsystems 60 (2018)
Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. CoRR (2017)
Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integr. 59 (2017)
Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
A LUT-Based Approximate Adder. FCCM (2016)
Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. 9 (4) (2016)
Thorbjörn Posewsky, Daniel Ziener
Efficient deep neural network acceleration through FPGA-based batch processing. ReConFig (2016)
Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT (2016)
Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich
A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT (2015)
Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS (2015)
Frank Hannig, Dirk Koch, Daniel Ziener
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR (2015)
Bernhard Schmidt, Daniel Ziener, Jürgen Teich
Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. IPDPS Workshops (2014)
Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. FCCM (2014)
Frank Hannig, Dirk Koch, Daniel Ziener
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR (2014)
Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL (2014)
Bernhard Schmidt, Daniel Ziener, Jürgen Teich
An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). FPGA (2014)
Christopher Dennl, Daniel Ziener, Jürgen Teich
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM (2013)
Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. 17 (2) (2013)
Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig (2012)
Christopher Dennl, Daniel Ziener, Jürgen Teich
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM (2012)
Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops (2012)
Stefan Wildermann, Jürgen Teich, Daniel Ziener
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL (2011)
Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
Stress-Aware Module Placement on Reconfigurable Devices. FPL (2011)
Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich
An FPGA implementation of a threat-based strategy for Connect6. FPT (2011)
Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS (2011)
Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT (2011)
Daniel Ziener, Florian Baueregger, Jürgen Teich
Using the Power Side Channel of FPGAs for Communication. FCCM (2010)
Daniel Ziener, Florian Baueregger, Jürgen Teich
Multiplexing Methods for Power Watermarking. HOST (2010)
Daniel Ziener, Jürgen Teich
New Directions for IP Core Watermarking and Identification. Dynamically Reconfigurable Architectures (2010)
Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich
A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE (2010)
Daniel Ziener, Jürgen Teich
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. J. Auton. Adapt. Commun. Syst. 2 (3) (2009)
Moritz Schmid, Daniel Ziener, Jürgen Teich
Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT (2008)
Daniel Ziener, Jürgen Teich
Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC (2008)
Daniel Ziener, Jürgen Teich
Power Signature Watermarking of IP Cores for FPGAs. J. Signal Process. Syst. 51 (1) (2008)
Daniel Ziener, Stefan Assmus, Jürgen Teich
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL (2006)
Daniel Ziener, Jürgen Teich
FPGA core watermarking based on power signature analysis. FPT (2006)

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Publication Activity (10 Years)

Top Topics

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Daniel Ziener