Walter Stechele

ORCID

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 69

Top Venues

Publications

Pierpaolo Morì, Shambhavi Balamuthu Sampath, Lukas Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Walter Stechele, Claudio Passerone
WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration. DAC (2023)
Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. ISQED (2023)
Jonas Kantic, Fabian C. Legl, Walter Stechele, Jakob Hermann
ReLiCADA - Reservoir Computing using Linear Cellular Automata Design Algorithm. CoRR (2023)
Zhongliang Jiang, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab
Skeleton Graph-Based Ultrasound-CT Non-Rigid Registration. IEEE Robotics Autom. Lett. 8 (8) (2023)
Zhongliang Jiang, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab
Skeleton Graph-based Ultrasound-CT Non-rigid Registration. CoRR (2023)
Manu Manuel, Benjamin Hien, Simon Conrady, Arne Kreddig, Nguyen Anh Vu Doan, Walter Stechele
Region of interest based non-dominated sorting genetic algorithm-II: an invite and conquer approach. GECCO (2022)
Furkan Kaynar, Peter Geißler, Laurent Demaret, Tamara Seybold, Walter Stechele
Non-iterative Blind Deblurring of Digital Microscope Images with Spatially Varying Blur. MIUA (2022)
Nael Fasfous, Lukas Frickenstein, Michael Neumeier, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Maurizio Martina, Walter Stechele
Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs. DATE (2022)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker, Walter Stechele
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. DATE (2022)
Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone
Accelerating and pruning CNNs for semantic segmentation on FPGA. DAC (2022)
Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab
Autonomous Robotic Screening of Tubular Structures Based Only on Real-Time Ultrasound Imaging Feedback. IEEE Trans. Ind. Electron. 69 (7) (2022)
Korbinian Weikl, Damien Schroeder, Walter Stechele
Potentials of combined visible light and near infrared imaging for driving automation. Autonomous Vehicles and Machines (2022)
Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Emanuele Valpreda, Manfredi Camalleri, Qi Zhao, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele
HW-Flow: A Multi-Abstraction Level HW-CNN Codesign Pruning Methodology. Leibniz Trans. Embed. Syst. 8 (1) (2022)
Manoj Rohit Vemparala, Nael Fasfous, Lukas Frickenstein, Alexander Frickenstein, Anmol Singh, Driton Salihu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization. BMVC (2021)
Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
BreakingBED - Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. CoRR (2021)
Ee Heng Chen, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Ahmed Mzid, Naveen Shankar Nagaraja, Jöran Zeisler, Walter Stechele
Investigating Binary Neural Networks for Traffic Sign Detection and Recognition. IV (2021)
Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
L2PF - Learning to Prune Faster. CoRR (2021)
Gábor Balázs, Mateusz Chmurski, Walter Stechele, Mariusz Zubert
Sensor Fusion Neural Networks for Gesture Recognition on Low-power Edge Devices. ICAART (2) (2021)
Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Sreetama Sarkar, Qi Zhao, Sabine Kuhn, Lukas Frickenstein, Anmol Singh, Christian Unger, Naveen Shankar Nagaraja, Christian Wressnegger, Walter Stechele
Adversarial Robust Model Compression Using In-Train Pruning. CVPR Workshops (2021)
Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
BreakingBED: Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. IntelliSys (1) (2021)
Korbinian Weikl, Damien Schroeder, Daniel Blau, Zhenyi Liu, Walter Stechele
End-to-End Imaging System Optimization for Computer Vision in Driving Automation. Autonomous Vehicles and Machines (2021)
Simon Conrady, Arne Kreddig, Manu Manuel, Nguyen Anh Vu Doan, Walter Stechele
Model-Based Design Space Exploration for FPGA-based Image Processing Applications Employing Parameterizable Approximations. Microprocess. Microsystems 87 (2021)
Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele
Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs. Int. J. Netw. Comput. 11 (2) (2021)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele
BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. CoRR (2021)
Arne Kreddig, Simon Conrady, Manu Manuel, Walter Stechele
A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA. DSD (2021)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Nguyen Anh Vu Doan, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele
HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology. ACM Trans. Embed. Comput. Syst. 20 (5s) (2021)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Mohamed Badawy, Walter Stechele
BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. IPDPS Workshops (2021)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour, Walter Stechele
Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. ICRA (2021)
Manoj Rohit Vemparala, Anmol Singh, Ahmed Mzid, Nael Fasfous, Alexander Frickenstein, Florain Mirus, Hans-Jörg Vögel, Naveen Shankar Nagaraja, Walter Stechele
Pruning CNNs for LiDAR-based Perception in Resource Constrained Environments. IV Workshops (2021)
Nguyen Anh Vu Doan, Manu Manuel, Simon Conrady, Arne Kreddig, Walter Stechele
Parameter Optimization of Approximate Image Processing Algorithms in FPGAs. CANDAR (Workshops) (2020)
Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. CoRR (2020)
Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. DAC (2020)
Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele
OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks. DATE (2020)
Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
L2PF - Learning to Prune Faster. CVIP (3) (2020)
Korbinian Weikl, Damien Schroeder, Walter Stechele
Optimization of automotive color filter arrays for traffic light color separation. CIC (2020)
Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab
Autonomous Robotic Screening of Tubular Structures based only on Real-Time Ultrasound Imaging Feedback. CoRR (2020)
Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele
Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. CoRR (2020)
Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele
Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. ICRA (2020)
Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele
Model-Based Design Space Exploration for Approximate Image Processing on FPGA. NorCAS (2020)
Gábor Balázs, Walter Stechele
Neural Architecture Search for Automotive Grid Fusion Networks Under Embedded Hardware Constraints. ICMLA (2020)
Simon Conrady, Manu Manuel, Arne Kreddig, Walter Stechele
LCS-based automatic configuration of approximate computing parameters for FPGA system designs. GECCO (Companion) (2019)
Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele
An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL. ARCS (2019)
Alexander Frickenstein, Manoj Rohit Vemparala, Christian Unger, Fatih Ayar, Walter Stechele
DSC: Dense-Sparse Convolution for Vectorized Inference of Convolutional Neural Networks. CVPR Workshops (2019)
Zhuangyi Jiang, Pengfei Xia, Kai Huang, Walter Stechele, Guang Chen, Zhenshan Bing, Alois C. Knoll
Mixed Frame-/Event-Driven Fast Pedestrian Detection. ICRA (2019)
Dirk Gabriel, Walter Stechele, Stefan Wildermann
Resource-Aware Parameter Tuning for Real-Time Applications. ARCS (2019)
Alexander Frickenstein, Christian Unger, Walter Stechele
Resource-Aware Optimization of DNNs for Embedded Applications. CRV (2019)
Gábor Balázs, Walter Stechele
Deep Grid Fusion of Feature-Level Sensor Data with Convolutional Neural Networks. ICCVE (2019)
Sebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid
Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base. ICCAD (2018)
Gereon Hinz, Guang Chen, Muhammad Aafaque, Florian Röhrbein, Jörg Conradt, Zhenshan Bing, Zhongnan Qu, Walter Stechele, Alois C. Knoll
Online Multi-object Tracking-by-Clustering for Intelligent Transportation System with Neuromorphic Vision Sensor. KI (2017)
Biao Hu, Uzair Sharif, Rajat Koner, Guang Chen, Kai Huang, Feihu Zhang, Walter Stechele, Alois C. Knoll
Random Finite Set Based Bayesian Filtering with OpenCL in a Heterogeneous Platform. Sensors 17 (4) (2017)
Stefan Tabel, Korbinian Weikl, Walter Stechele
Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter. ASAP (2017)
Erol Koser, Korbinian Berthold, Ravi Kumar Pujari, Walter Stechele
A Chip-level Redundant Threading (CRT) scheme for shared-memory protection. HPCS (2016)
Walter Stechele, Tomasz Kryjak, Lionel Lacassagne, Dominique Houzet, Martin Danek
Special session 1 automotive parallel computing challenges - architectures, applications and tricks. DASIP (2016)
Erol Koser, Sebastian Krosche, Walter Stechele
Integrated Soft Error Resilience and Self-Test. VLSI-SoC (2016)
Kyunghun Lee, Haifa Ben Salem, Thyagaraju Damarla, Walter Stechele, Shuvra S. Bhattacharyya
Prototyping real-time tracking systems on mobile devices. Conf. Computing Frontiers (2016)
Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
Preface. FPL (2016)
Erol Koser, Walter Stechele
Tackling long duration transients in sequential logic. IOLTS (2016)
Haifa Ben Salem, Thyagaraju Damarla, Kishan Sudusinghe, Walter Stechele, Shuvra S. Bhattacharyya
Adaptive tracking of people and vehicles using mobile platforms. EURASIP J. Adv. Signal Process. 2016 (2016)
Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. 58 (6) (2016)
David May, Walter Stechele
Voltage over-scaling in sequential circuits for approximate computing. DTIS (2016)
Erol Koser, Felix Miller, Walter Stechele
Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic. DSD (2015)
Johny Paul, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Manfred Kröhnert, Daniel Lohmann, Walter Stechele, Tamim Asfour, Wolfgang Schröder-Preikschat
Self-adaptive corner detection on MPSoC through resource-aware programming. J. Syst. Archit. 61 (10) (2015)
Walter Stechele
Protecting FPGA-based automotive systems against soft errors through reduced precision redundancy. SIES (2015)
Tamara Seybold, Mathias Plichta, Walter Stechele
Improving wavelet denoising based on an in-depth analysis of the camera color processing. Real-Time Image and Video Processing (2015)
David May, Walter Stechele
Design of fine-grained sequential approximate circuits using probability-aware fault emulation. ISLPED (2015)
Johny Paul, Walter Stechele
Predictability of image processing algorithms on heterogeneous MPSoC. ESTIMedia (2015)
Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61 (10) (2015)
Raphael Polig, Heiner Giefers, Walter Stechele
A soft-core processor array for relational operators. ASAP (2015)
Jan Frost, Walter Stechele, Erik Maehle
Self-reconfigurable control architecture for complex mobile robots. it Inf. Technol. 57 (2) (2015)
Tamara Seybold, Florian Kuhn, Julian Habigt, Mark Hartenstein, Walter Stechele
Automatic denoising parameter estimation using gradient histograms. VCIP (2014)
Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP (2014)
Michael Frischke, Andreas J. Rohatschek, Walter Stechele
Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems. IOLTS (2014)
Tamara Seybold, Özlem Cakmak, Christian Keimel, Walter Stechele
Noise characteristics of a single sensor camera in digital color image processing. CIC (2014)
Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour
Resource-Aware Programming for Robotic Vision. CoRR (2014)
Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele, Tamim Asfour
Resource Prediction for Humanoid Robots. CoRR (2014)
David May, Walter Stechele
Improving the significance of probabilistic circuit fault emulations. IOLTS (2014)
Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat
Resource-Aware Harris Corner Detection Based on Adaptive Pruning. ARCS (2014)
Tamara Seybold, Marion Knopp, Christian Keimel, Walter Stechele
Beyond Standard Noise Models: Evaluating Denoising Algorithms with Respect to Realistic Camera Noise. Int. J. Semantic Comput. 8 (2) (2014)
Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour
Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories. ARCS Workshops (2014)
Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. FPL (2013)
Tamara Seybold, Christian Keimel, Marion Knopp, Walter Stechele
Towards an Evaluation of Denoising Algorithms with Respect to Realistic Camera Noise. ISM (2013)
Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat
A resource-aware nearest-neighbor search algorithm for k-dimensional trees. DASIP (2013)
Johny Paul, Andreas Laika, Christopher Claus, Walter Stechele, Adam El Sayed Auf, Erik Maehle
Real-time motion detection based on SW/HW-codesign for walking rescue robots. J. Real Time Image Process. 8 (4) (2013)
Jan Hartmann, Walter Stechele, Erik Maehle
Self-reconfigurable Control Architecture for Complex Robots. GI-Jahrestagung (2013)
Michael Vonbun, Stefan Wallentowitz, Michael Feilen, Walter Stechele, Andreas Herkersdorf
Evaluation of hop count advantages of network-coded 2D-mesh NoCs. PATMOS (2013)
Jan Hartmann, Walter Stechele, Erik Maehle
Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles. ARCS (2013)
Gregor Walla, Zaur Molotnikov, Hans-Ulrich Michel, Walter Stechele, Andreas Barthels, Andreas Herkersdorf
A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management. ECMS (2013)
Florian Aschauer, Walter Stechele, Johannes Treis
FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer. DSD (2013)
Florian Aschauer, Walter Stechele, Johannes Treis
Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs. DSD (2013)
David May, Walter Stechele
A resource-efficient probabilistic fault simulator. FPL (2013)
Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib
Potentials and Challenges for Multi-Core Processors in Robotic Applications. GI-Jahrestagung (2013)
Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. IPDPS Workshops (2013)
Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele
Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. FPL (2012)
Lothar Stolz, Matthias Ihmig, Walter Stechele
An evaluation on using GPU coprocessing for software radios on a low-cost platform. DASIP (2012)
Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS (2012)
Michael Feilen, Andreas Iliopoulos, Matthias Ihmig, Walter Stechele
Partitioning and context switching for a reconfigurable FPGA-based DAB receiver. DASIP (2012)
Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Rüdiger Dillmann
Invasive Computing for robotic vision. ASP-DAC (2012)
David May, Walter Stechele
An FPGA-based probability-aware fault simulator. ICSAMOS (2012)
Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops (2012)
Sebastian Drössler, Michael Eichhorn, S. Holzknecht, Bernd Müller-Rathgeber, Holm Rauchfuss, Michael Zwick, Erwin M. Biebl, Klaus Diepold, Jörg Eberspächer, Andreas Herkersdorf, Walter Stechele, Eckehard G. Steinbach, R. Freymann, Karl-Ernst Steinberg, Hans-Ulrich Michel
A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems. Advances in Real-Time Systems (2012)

Walter Stechele.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Walter Stechele