Lars Bauer

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 50

Top Venues

DATE

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DAC

CoRR

Karlsruhe Institute of Technology (PHD)

Education History

Karlsruhe Institute of Technology

PHD

Publications

Lilas Alrahis, Hassan Nassar, Jonas Krautter, Dennis Gnad, Lars Bauer, Jörg Henkel, Mehdi B. Tahoori
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs. HOST (2024)
Jeferson González-Gómez, Hassan Nassar, Lars Bauer, Jörg Henkel
LightFAt: Mitigating Control-flow Explosion via Lightweight PMU-based Control-flow Attestation. CoRR (2024)
Jeferson González-Gómez, Hassan Nassar, Lars Bauer, Jörg Henkel
LightFAt: Mitigating Control-Flow Explosion via Lightweight PMU-Based Control-Flow Attestation. HOST (2024)
Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel
Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels. FPGA (2024)
Lilas Alrahis, Hassan Nassar, Jonas Krautter, Dennis Gnad, Lars Bauer, Jörg Henkel, Mehdi B. Tahoori
MaliGNNoma: GNN-Based Malicious Circuit Classifier for Secure Cloud FPGAs. CoRR (2024)
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES (2023)
Jeferson González-Gómez, Kevin Cordero-Zuñiga, Lars Bauer, Jörg Henkel
The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and Countermeasures. DATE (2023)
Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen, Jörg Henkel
Swift-CNN: Leveraging PCM Memory's Fast Write Mode to Accelerate CNNs. IEEE Embed. Syst. Lett. 15 (4) (2023)
Hassan Nassar, Lars Bauer, Jörg Henkel
Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators. IEEE Embed. Syst. Lett. 15 (4) (2023)
Hassan Nassar, Lars Bauer, Jörg Henkel
ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF. ACM Trans. Embed. Comput. Syst. 22 (5s) (2023)
Nils Hölscher, Christian Hakert, Hassan Nassar, Kuan-Hsun Chen, Lars Bauer, Jian-Jia Chen, Jörg Henkel
Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Hassan Nassar, Simon Pankner, Lars Bauer, Jörg Henkel
Late Breaking Results: Configurable Ring Oscillators as a Side-Channel Countermeasure. DAC (2023)
Jeferson González-Gómez, Mohammed Bakr Sikal, Heba Khdr, Lars Bauer, Jörg Henkel
Smart Detection of Obfuscated Thermal Covert Channel Attacks in Many-core Processors. DAC (2023)
Hassan Nassar, Rafik Youssef, Lars Bauer, Jörg Henkel
Supporting Dynamic Control-Flow Execution for Runtime Reconfigurable Processors. ICM (2023)
Jeferson González-Gómez, Lars Bauer, Jörg Henkel
Cache-Based Side-Channel Attack Mitigation for Many-Core Distributed Systems via Dynamic Task Migration. IEEE Trans. Inf. Forensics Secur. 18 (2023)
Hassan Nassar, Lars Bauer, Jörg Henkel
CaPUF: Cascaded PUF Structure for Machine Learning Resiliency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Volker Wenzel, Lars Bauer, Wolfgang Schröder-Preikschat, Jörg Henkel
Agent-based Constraint Solving for Resource Allocation in Manycore Systems. CoRR (2022)
Ali Asghar Mohammad Salehi, Bardia Safaei, Amir Mahdi Hosseini Monazzah, Lars Bauer, Jörg Henkel, Alireza Ejlali
ARMOR: A Reliable and Mobility-Aware RPL for Mobile Internet of Things Infrastructures. IEEE Internet Things J. 9 (2) (2022)
Christian Hakert, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brüggen, Hussam Amrouch, Jörg Henkel, Jian-Jia Chen
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory. ACM Trans. Embed. Comput. Syst. 21 (1) (2022)
Hassan Nassar, Lars Bauer, Jörg Henkel
TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation. DATE (2021)
Hassan Nassar, Hanna AlZughbi, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel
LoopBreaker: Disabling Interconnects to Mitigate Voltage-Based Attacks in Multi-Tenant FPGAs. ICCAD (2021)
Tatsuji Munaka, Farzad Samie, Lars Bauer, Jörg Henkel
Improved Feature Extraction Method for Sound Recognition Applied to Automatic Sorting of Recycling Wastes. J. Inf. Process. 28 (2020)
Florian Schmaus, Sebastian Maier, Tobias Langer, Jonas Rabenstein, Timo Hönig, Wolfgang Schröder-Preikschat, Lars Bauer, Jörg Henkel
System Software for Resource Arbitration on Future Many-* Architectures. IPDPS Workshops (2020)
Bardia Safaei, Ali Asghar Mohammadsalehi, Kimia Talaei Khoosani, Saba Zarbaf, Amir Mahdi Hosseini Monazzah, Farzad Samie, Lars Bauer, Jörg Henkel, Alireza Ejlali
Impacts of Mobility Models on RPL-Based Mobile IoT Infrastructures: An Evaluative Comparison and Survey. IEEE Access 8 (2020)
Christian Hakert, Kuan-Hsun Chen, Paul R. Genssler, Georg von der Brüggen, Lars Bauer, Hussam Amrouch, Jian-Jia Chen, Jörg Henkel
SoftWear: Software-Only In-Memory Wear-Leveling for Non-Volatile Main Memory. CoRR (2020)
Farzad Samie, Vasileios Tsoutsouras, Dimosthenis Masouros, Lars Bauer, Dimitrios Soudris, Jörg Henkel
Fast Operation Mode Selection for Highly Efficient IoT Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Farzad Samie, Lars Bauer, Jörg Henkel
Hierarchical Classification for Constrained IoT Devices: A Case Study on Human Activity Recognition. IEEE Internet Things J. 7 (9) (2020)
Lars Bauer, Marvin Damschen, Dirk Ziegenbein, Arne Hamann, Alessandro Biondi, Giorgio C. Buttazzo, Jörg Henkel
Analyses and architectures for mixed-critical systems: industry trends and research perspective. EMSOFT Companion (2019)
Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel
: Optimizing Operation-mode Selection for IoT Edge Devices. ACM Trans. Internet Techn. 19 (2) (2019)
Manolis Katsaragakis, Dimosthenis Masouros, Vasileios Tsoutsouras, Farzad Samie, Lars Bauer, Jörg Henkel, Dimitrios Soudris
DMRM: Distributed Market-Based Resource Management of Edge Computing Systems. DATE (2019)
Marvin Damschen, Lars Bauer, Jörg Henkel
WCET Guarantees for Opportunistic Runtime Reconfiguration. ICCAD (2019)
Farzad Samie, Lars Bauer, Jörg Henkel
From Cloud Down to Things: An Overview of Machine Learning in Internet of Things. IEEE Internet Things J. 6 (3) (2019)
Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel
Distributed Trade-Based Edge Device Management in Multi-Gateway IoT. ACM Trans. Cyber Phys. Syst. 2 (3) (2018)
Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio C. Buttazzo, Jörg Henkel
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs. ACM Trans. Reconfigurable Technol. Syst. 11 (2) (2018)
Farzad Samie, Sebastian Paul, Lars Bauer, Jörg Henkel
Highly efficient and accurate seizure prediction on constrained IoT devices. DATE (2018)
Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC (2017)
Jörg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). DATE (2017)
Marvin Damschen, Lars Bauer, Jörg Henkel
CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems. IEEE Embed. Syst. Lett. 9 (3) (2017)
Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat, Michael Bader
Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing. Euro-Par Workshops (2017)
Marvin Damschen, Lars Bauer, Jörg Henkel
Timing Analysis of Tasks on Runtime Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jörg Henkel
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. IEEE Trans. Computers 66 (6) (2017)
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Hongyan Zhang, Lars Bauer, Jörg Henkel
Resource budgeting for reliability in reconfigurable architectures. DAC (2016)
Marvin Damschen, Lars Bauer, Jörg Henkel
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors. ACM Trans. Archit. Code Optim. 13 (4) (2016)
Farzad Samie, Lars Bauer, Jörg Henkel
IoT technologies for embedded computing: a survey. CODES+ISSS (2016)
Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel
Computation offloading and resource allocation for low-power IoT edge devices. WF-IoT (2016)
Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58 (6) (2016)
Fazal Hameed, Lars Bauer, Jörg Henkel
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (4) (2016)
Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. 58 (6) (2016)
Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris, Jörg Henkel
Distributed QoS management for internet of things under resource constraints. CODES+ISSS (2016)
Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare, Jörg Henkel
Floating point acceleration for stream processing applications in dynamically reconfigurable processors. ESTIMedia (2015)
Farzad Samie, Lars Bauer, Jörg Henkel
An approximate compressor for wearable biomedical healthcare monitoring systems. CODES+ISSS (2015)
Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang
Adaptive multi-layer techniques for increased system dependability. it Inf. Technol. 57 (3) (2015)
Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel
Multicast FullHD H.264 Intra Video Encoder Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (12) (2015)
Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61 (10) (2015)
Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel
Online binding of applications to multiple clock domains in shared FPGA-based systems. DATE (2015)
Sebastian Kobbe, Lars Bauer, Jörg Henkel
Adaptive on-the-fly application performance modeling for many cores. DATE (2015)
Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. ICCAD (2015)
Muhammad Shafique, Lars Bauer, Jörg Henkel
Adaptive Energy Management for Dynamically Reconfigurable Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Martin Haaß, Lars Bauer, Jörg Henkel
Automatic custom instruction identification in memory streaming algorithms. CASES (2014)
Fazal Hameed, Lars Bauer, Jörg Henkel
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. DAC (2014)
Jörg Henkel, Lars Bauer, Artjom Grudnitsky, Hongyan Zhang
-core. SIGBED Rev. 11 (3) (2014)
Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. DAC (2014)
Jörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique
Multi-Layer Dependability: From Microarchitecture to Application Level. DAC (2014)
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
MORP: makespan optimization for processors with an embedded reconfigurable fabric. FPGA (2014)
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems. CASES (2014)
Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich
Test Strategies for Reliable Runtime Reconfigurable Architectures. IEEE Trans. Computers 62 (8) (2013)
Fazal Hameed, Lars Bauer, Jörg Henkel
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. CODES+ISSS (2013)
Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn
Reliable on-chip systems in the nano-era: lessons learnt and future trends. DAC (2013)
Fazal Hameed, Lars Bauer, Jörg Henkel
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies. CASES (2013)
Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. ITC (2013)
Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel
An H.264 Quad-FullHD low-latency intra video encoder. DATE (2013)
Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel
Hardware acceleration for programs in SSA form. CASES (2013)
Fazal Hameed, Lars Bauer, Jörg Henkel
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. DATE (2013)
Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel
PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors. FCCM (2012)
Fazal Hameed, Lars Bauer, Jörg Henkel
Dynamic cache management in multi-core architectures through run-time adaptation. DATE (2012)
Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". AHS (2012)
Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich
Transparent structural online test for reconfigurable systems. IOLTS (2012)
Artjom Grudnitsky, Lars Bauer, Jörg Henkel
Partial online-synthesis for mixed-grained reconfigurable architectures. DATE (2012)
Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe
Invasive manycore architectures. ASP-DAC (2012)
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors. CODES+ISSS (2011)
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. FCCM (2011)
Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions. DATE (2011)
Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfgang Schröder-Preikschat, Jörg Henkel
DistRM: distributed resource management for on-chip many-core systems. CODES+ISSS (2011)
Lars Bauer, Muhammad Shafique, Jörg Henkel
Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors. AHS (2011)
Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
Design and architectures for dependable embedded systems. CODES+ISSS (2011)
Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jörg Henkel
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors. DATE (2011)
Muhammad Shafique, Lars Bauer, Jörg Henkel
Selective instruction set muting for energy-aware adaptive processors. ICCAD (2010)
Muhammad Shafique, Lars Bauer, Jörg Henkel
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. DATE (2010)
Muhammad Shafique, Lars Bauer, Jörg Henkel
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms. J. Signal Process. Syst. 60 (2) (2010)
Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. DATE (2010)
Muhammad Shafique, Lars Bauer, Jörg Henkel
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. ICCAD (2009)
Lars Bauer, Muhammad Shafique, Jörg Henkel
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. CODES+ISSS (2009)
Lars Bauer, Muhammad Shafique, Jörg Henkel
RISPP: A run-time adaptive reconfigurable embedded processor. FPL (2009)
Muhammad Shafique, Lars Bauer, Jörg Henkel
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. DATE (2009)
Lars Bauer, Muhammad Shafique, Jörg Henkel
Cross-architectural design space exploration tool for reconfigurable processors. DATE (2009)
Lars Bauer, Muhammad Shafique, Jörg Henkel
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 16 (10) (2008)
Lars Bauer, Muhammad Shafique, Jörg Henkel
Run-time instruction set selection in a transmutable embedded processor. DAC (2008)
Muhammad Shafique, Lars Bauer, Jörg Henkel
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. ISLPED (2008)
Lars Bauer, Muhammad Shafique, Jörg Henkel
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. FPL (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Lars Bauer