Carsten Tradowsky

Publication Activity (10 Years)

Years Active: 2011-2017
Publications (10 Years): 6

Top Venues

ARC

ARCS

ISSoC

ReConFig

Karlsruhe Institute of Technology, Germany (PHD)

Education History

Karlsruhe Institute of Technology, Germany

PHD

Publications

Manuel Mohr, Carsten Tradowsky
Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores. DATE (2017)
Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC (2017)
Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
Adaptive Cache Structures. ARCS (2016)
Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. ARC (2016)
Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC (2015)
Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC (2015)
Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker
Towards Dynamic Cache and Bandwidth Invasion. ARC (2014)
Carsten Tradowsky, Tobias Gädeke, Thomas Bruckschlögl, Wilhelm Stork, Klaus D. Müller-Glaser, Jürgen Becker
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. PDP (2014)
Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker
LImbiC: An adaptable architecture description language model for developing an application-specific image processor. ISVLSI (2013)
Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC (2013)
Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker
Adaptive processor architecture - invited paper. ICSAMOS (2012)
Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES (2012)
Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops (2012)
Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker
Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig (2012)
Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker
Dynamic Processor Reconfiguration. ReConFig (2011)

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Publication Activity (10 Years)

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Carsten Tradowsky