Peter Figuli

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 9

Top Topics

Design Space Exploration

Reconfigurable Architecture

Signal Processing

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Cédric Lichtenau, Alper Buyuktosunoglu, Ramon Bertran, Peter Figuli, Christian Jacobi, Nikolaos Papandreou, Haris Pozidis, Anthony Saporito, Andrew Sica, Elpida Tzortzatos
AI accelerator on IBM telum processor: industrial product. ISCA (2022)
Shalina Percy Delicia Figuli, Peter Figuli, Jürgen Becker
A reconfigurable high-speed spiral FIR filter architecture. TSP (2017)
Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
Parameter Sensitivity in Virtual FPGA Architectures. ARC (2017)
Matthias Birk, Ernst Kretzek, Peter Figuli, Marc Weber, Jürgen Becker, Nicole V. Ruiter
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. IEEE Trans. Parallel Distributed Syst. 27 (2) (2016)
Shalina Percy Delicia Figuli, Alberto Sonnino, Peter Figuli, Jürgen Becker
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing. TSP (2016)
Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC (2015)
Shalina Percy Delicia, George Ford, Peter Figuli, Jürgen Becker
Parametric design space exploration for optimizing QAM based high-speed communication. ICCC (2015)
Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC (2015)
Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS (2015)
Harry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. FPL (2013)
Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker
JITPR: A framework for supporting fast application's implementation onto FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6 (2) (2013)
Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC (2013)
Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner
On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation. IPDPS Workshops (2012)
Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios, Jürgen Becker
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops (2011)
Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker
A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS (2011)