George Economakos

Publication Activity (10 Years)

Years Active: 1995-2016
Publications (10 Years): 10

Top Topics

Magnetic Resonance Imaging

Hardware Design

Heterogeneous Systems

Rapid Prototyping

Top Venues

ACM Trans. Embed. Comput. Syst.

Panhellenic Conference on Informatics

Publications

Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis. ACM Trans. Embed. Comput. Syst. 16 (1) (2016)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems. ACM Trans. Embed. Comput. Syst. 15 (3) (2016)
Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios, George Economakos, Dimitrios Soudris, Jürgen Becker
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. SAMOS (2016)
Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. ARC (2015)
Christoforos E. Economakos, Maria P. Tzamtzi, Michael G. Skarpetis, George Economakos
Performance improvements in a modern hardware design environment for control applications. ICIT (2015)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos
A virtual platform for exploring hierarchical interconnection for many-accelerator systems. SAMOS (2015)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. FPL (2015)
Efthymia Kazakou, George Economakos
Comparison of OpenCL based design for a medical device on heterogeneous architectures with CPU, GPU and FPGA. Panhellenic Conference on Informatics (2015)
Christoforos E. Economakos, George Kiokes, George Economakos
Using advanced FPGA SoC technologies for the design of industrial control applications. IISA (2015)
Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS (2015)
Dimitris Bekiaris, Sotirios Xydis, George Economakos
Systematic Design and Evaluation of Reconfigurable Arithmetic Components in the Deep submicron Domain. J. Circuits Syst. Comput. 23 (10) (2014)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging. MobiHealth (2014)
Dionysios Diamantopoulos, Efstathios Sotiriou-Xanthopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs. ACM Trans. Embed. Comput. Syst. 13 (5s) (2014)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks. PARMA-DITAM@HiPEAC (2014)
Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
A framework for rapid evaluation of heterogeneous 3-D NoC architectures. Microprocess. Microsystems 38 (4) (2014)
Christoforos E. Economakos, Maria P. Tzamtzi, George Economakos
A scalable FPGA-based architecture for digital controllers and a corresponding rapid prototyping design methodology. ISIE (2014)
Christoforos E. Economakos, Michael G. Skarpetis, George Economakos
Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures. ICINCO (1) (2014)
Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos
Co-design of many-accelerator heterogeneous systems exploiting virtual platforms. ICSAMOS (2014)
Dionysios Diamantopoulos, George Economakos, Dionysios I. Reisis
Using high-level synthesis to build memory and datapath optimized DSP accelerators. ICECS (2014)
Christoforos E. Economakos, Harry Sidiropoulos, George Economakos
Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies. ICAC (2013)
Dionysios Diamantopoulos, Christoforos E. Economakos, Dimitrios Soudris, George Economakos
A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs? ISSPIT (2013)
Efstathios Sotiriou-Xanthopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris
A Process-based Reconfigurable SystemC Module for simulation speedup. ICSAMOS (2013)
Dionysios Diamantopoulos, Kostas Siozios, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris
HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips. IPDPS Workshops (2013)
Harry Sidiropoulos, Efthymia Kazakou, Christoforos E. Economakos, George Economakos
Efficient C level hardware design for floating point biomedical DSP applications. BIBE (2013)
Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Alexandros Bartzas, George Economakos
A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures. Euro-Par Workshops (2012)
George Economakos
ESL as a Gateway from OpenCL to FPGAs: Basic Ideas and Methodology Evaluation. Panhellenic Conference on Informatics (2012)
Dimitris Bekiaris, George Economakos
Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain. DSD (2012)
Dimitris Bekiaris, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris
Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments. ReCoSoC (2012)
Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos, Dimitrios Soudris
Design and experimentation with low-power morphable multipliers. ICECS (2011)
Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi
High Performance and Area Efficient Flexible DSP Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris
Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow. ReConFig (2011)
Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures. ISVLSI (2010)
Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. ISVLSI (Selected papers) (2010)
Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. ISVLSI (2010)
Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. PATMOS (2010)
Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. ISCAS (2010)
Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris
BIT-width exploration over 3D architectures using high-level synthesis. ICECS (2010)
Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos
High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. ISVLSI (2010)
George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris
Construction of dual mode components for reconfiguration aware high-level synthesis. DATE (2010)
George Economakos
Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology. EUSIPCO (2009)
Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi
Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. AHS (2009)
George Economakos, Sotirios Xydis
High-level synthesis with coarse grain reconfigurable components. IPDPS (2009)
Kostas Siozios, Dimitrios Soudris, George Economakos
Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations. DPS (2009)
George Kiokes, George Economakos, Angelos Amditis, Nikolaos K. Uzunoglu
Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. DSD (2009)
Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. ICECS (2009)
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
Extending an embedded RISC microprocessor for efficient translation based Java execution. Microprocess. Microsystems 33 (7-8) (2009)
Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. Integr. 42 (4) (2009)
George Economakos, Sotirios Xydis
Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. DSD (2009)
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
An instruction set extension for java bytecodes translation acceleration. ICSAMOS (2008)
George Economakos, Sotirios Xydis
A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. DSD (2008)
Sotirios Xydis, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability. EUSIPCO (2008)
Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi
Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. AHS (2008)
Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos
A predecoding technique for ILP exploitation in Java processors. J. Syst. Archit. 54 (7) (2008)
Christoforos E. Economakos, George Economakos
Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. ETFA (2008)
Dimitris Bekiaris, George Economakos, Kiamal Z. Pekmestzi
Efficient serial and parallel implementation of programmable fir filters based on the merging technique. EUSIPCO (2008)
George Economakos
Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. BIBE (2008)
Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS (2007)
George Economakos, Sotirios Xydis
High-level synthesis heuristics for run-time reconfigurable architectures. EUSIPCO (2007)
George Economakos, Christoforos E. Economakos, Sotirios Xydis
Run-time reconfigurable solutions for adaptive control applications. ICINCO-SPSMC (2007)
Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. ICECS (2007)
Isidoros Sideris, Dimitris Pilitsos, George Economakos, Kiamal Z. Pekmestzi
Building embedded DSP applications in a Java modeling framework. EUSIPCO (2007)
Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS (2007)
Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi
A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware. EUSIPCO (2007)
George Economakos
Behavioral synthesis with SystemC and PSL assertions for interface specification. ISCAS (2006)
George Economakos, Kostas Anagnostopoulos
Bit level architectural exploration technique for the design of low power multipliers. ISCAS (2006)
George Economakos
High-level synthesis with reconfigurable datapath components. IPDPS (2006)
George Economakos, Kostas Anagnostopoulos, Isidoros Sideris
A Methodology for Design Space Exploration in Embedded DSP Applications. ICECS (2006)
Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi
A cache based stack folding technique for high performance Java processors. JTRES (2006)
Konstantinos Anagnostopoulos, George Economakos
Lowpower design of multipliers using a full-adder isolation technique. ICECS (2005)
George Economakos, Petros Oikonomakos, Ioannis Poulakis, George K. Papakonstantinou, Stamatis Georgoulis
Handling advanced scheduling heuristics under a hardware compiler generation environment. Knowl. Based Syst. 15 (1-2) (2002)
George Economakos, Stergios Stergiou, George K. Papakonstantinou, Vassilios Zoukos
A Multi-Lingual Synthesis and Verification Environment. DSD (2001)
George Economakos, Petros Oikonomakos, Ioannis Panagopoulos, Ioannis Poulakis, George K. Papakonstantinou
Behavioral synthesis with systemC. DATE (2001)
George Economakos, Ioannis Drositis, George K. Papakonstantinou
A complete specification and implementation methodology for high-level hardware transformations. ICECS (2000)
Ioannis Poulakis, Petros Economakos, George Economakos, Ioannis Panagopoulos, George K. Papakonstantinou
A top-down interactive behavioral synthesis environment. ICECS (2000)
George Economakos, George K. Papakonstantinou
Language Based Design Verification with Semantic Analysis. EUROMICRO (1999)
George Economakos, George K. Papakonstantinou
A formal method for hardware design using attribute grammars. ICECS (1999)
George Economakos, George K. Papakonstantinou
Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. CHARME (1999)
George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. SAC (1998)
George Economakos, George K. Papakonstantinou, Panayiotis Tsanakas
Behavioral synthesis of digital filters using attribute grammars. EUSIPCO (1998)
George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. DATE (1998)
George Economakos, George K. Papakonstantinou
Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. EUROMICRO (1998)
Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. HPCN Europe (1997)
George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas
Hardware compilation using attribute grammars. CHARME (1997)
George Economakos, George K. Papakonstantinou, Panayotis Tsanakas
An attribute grammar approach to high-level automated hardware synthesis. Inf. Softw. Technol. 37 (9) (1995)