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High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.
Sotirios Xydis
Kiamal Z. Pekmestzi
Dimitrios Soudris
George Economakos
Published in:
ISVLSI (2010)
Keyphrases
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coarse grained
high level synthesis
fine grained
shared memory
massively parallel
parallel architecture
hardware implementation
energy landscape
high level
functional units
artificial intelligence
access control
protein sequences
design space exploration
distributed memory