Bit level architectural exploration technique for the design of low power multipliers.
George EconomakosKostas AnagnostopoulosPublished in: ISCAS (2006)
Keyphrases
- low power
- single chip
- low cost
- low power consumption
- power consumption
- vlsi architecture
- logic circuits
- high speed
- mixed signal
- digital signal processing
- vlsi circuits
- gate array
- cmos technology
- power reduction
- design process
- real time
- power dissipation
- image sensor
- software architecture
- circuit design
- wireless transmission
- nm technology
- analog to digital converter