CHARME

Keyphrases

Publications

2005

Warren A. Hunt Jr., Erik Reeber
Formalization of the DE2 Language. CHARME (2005)
David Ward, Fabio Somenzi
Automatic Generation of Hints for Symbolic Traversal. CHARME (2005)
Arindam Chakrabarti, Krishnendu Chatterjee, Thomas A. Henzinger, Orna Kupferman, Rupak Majumdar
Verifying Quantitative Properties Using Bound Functions. CHARME (2005)
Ou Wei, Arie Gurfinkel, Marsha Chechik
Identification and Counter Abstraction for Full Virtual Symmetry. CHARME (2005)
Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
Predictive Reachability Using a Sample-Based Approach. CHARME (2005)
Daniel Große, Rolf Drechsler
Acceleration of SAT-Based Iterative Property Checking. CHARME (2005)
Hari Mony, Jason Baumgartner, Adnan Aziz
Exploiting Constraints in Transformation-Based Verification. CHARME (2005)
Tsachy Kapschitz, Ran Ginosar
Formal Verification of Synchronizers. CHARME (2005)
Sudhindra Pandav, Konrad Slind, Ganesh Gopalakrishnan
Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification. CHARME (2005)
Emil Axelsson, Koen Claessen, Mary Sheeran
Wired: Wire-Aware Circuit Design. CHARME (2005)
Jan-Willem Roorda, Koen Claessen
A New SAT-Based Algorithm for Symbolic Trajectory Evaluation. CHARME (2005)
Nina Amla, Xiaoqun Du, Andreas Kuehlmann, Robert P. Kurshan, Kenneth L. McMillan
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment. CHARME (2005)
Hana Chockler, Kathi Fisler
Temporal Modalities for Concisely Capturing Timing Diagrams. CHARME (2005)
Petr Matousek, Ales Smrcka, Tomás Vojnar
High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. CHARME (2005)
Wolfram Büttner
Is Formal Verification Bound to Remain a Junior Partner of Simulation? CHARME (2005)
Katell Morin-Allory, David Cachera
Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic. CHARME (2005)
Gianfranco Ciardo, Andy Jinqing Yu
Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning. CHARME (2005)
Masahiro Fujita
Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths. CHARME (2005)
Oliver Pell, Wayne Luk
Resolving Quartz Overloading. CHARME (2005)
Stefan Staber, Barbara Jobstmann, Roderick Bloem
Finding and Fixing Faults. CHARME (2005)
Masaharu Imai, Akira Kitajima
Verification Challenges in Configurable Processor Design with ASIP Meister. CHARME (2005)
Miroslav N. Velev
Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. CHARME (2005)
Mona Safar, M. Watheq El-Kharashi, Ashraf Salem
FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers. CHARME (2005)
Leslie Lamport
Real-Time Model Checking Is Really Simple. CHARME (2005)
Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster
Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation. CHARME (2005)
Christian Ferdinand, Reinhold Heckmann
Verifying Timing Behavior by Abstract Interpretation of Executable Code. CHARME (2005)
ShengYu Shen, Ying Qin, Sikun Li
Minimizing Counterexample of ACTL Property. CHARME (2005)
Arie Gurfinkel, Marsha Chechik
How Thorough Is Thorough Enough? CHARME (2005)
Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
Error Detection Using BMC in a Parallel Environment. CHARME (2005)
Thomas In der Rieden, Dirk Leinenbach, Wolfgang J. Paul
Towards the Pervasive Verification of Automotive Systems. CHARME (2005)
João P. Marques Silva
Improvements to the Implementation of Interpolant-Based Model Checking. CHARME (2005)
William D. Young
Introducing Abstractions via Rewriting. CHARME (2005)
Alex Tsow, Steven D. Johnson
Data Refinement for Synchronous System Specification and Construction. CHARME (2005)
Viresh Paruthi, Christian Jacobi, Kai Weber
Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting. CHARME (2005)
Doron Bustan, Alon Flaisher, Orna Grumberg, Orna Kupferman, Moshe Y. Vardi
Regular Vacuity. CHARME (2005)
Emmanuel Zarpas
A Case Study: Formal Verification of Processor Critical Properties. CHARME (2005)
Jason Baumgartner, Hari Mony
Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies. CHARME (2005)
Liang Zhang, Mukul R. Prasad, Michael S. Hsiao
Interleaved Invariant Checking with Dynamic Abstraction. CHARME (2005)
Biniam Gebremichael, Frits W. Vaandrager, Miaomiao Zhang, Kees Goossens, Edwin Rijpkema, Andrei Radulescu
Deadlock Prevention in the Æthereal Protocol. CHARME (2005)
Iakov Dalinger, Mark A. Hillebrand, Wolfgang J. Paul
On the Verification of Memory Management Mechanisms. CHARME (2005)
Panagiotis Manolios, Sudarshan K. Srinivasan
A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME (2005)
Ritwik Bhattacharya, Steven M. German, Ganesh Gopalakrishnan
Symbolic Partial Order Reduction for Rule Based Transition Systems. CHARME (2005)

volume 3725, 2005

Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings CHARME 3725 (2005)

2003

volume 2860, 2003

Correct Hardware Design and Verification Methods, 12th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2003, L'Aquila, Italy, October 21-24, 2003, Proceedings CHARME 2860 (2003)