Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
Fazal HameedLars BauerJörg HenkelPublished in: DAC (2014)
Keyphrases
- dynamic random access memory
- prefetching
- memory subsystem
- main memory
- memory hierarchy
- hit rate
- embedded dram
- hit ratio
- data access
- caching scheme
- user perceived latency
- replacement policy
- response time
- query processing
- web caching
- real time
- access patterns
- memory access
- data structure
- ibm zenterprise
- random access memory
- multithreading
- power consumption
- input output
- management system