Hsiang-Yun Cheng

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 25

Top Topics

Efficient Inference

Storage Devices

Top Venues

Publications

Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. DATE (2024)
Tsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. DATE (2024)
Hao-Wei Chiang, Chin-Fu Nien, Hsiang-Yun Cheng, Kuei-Po Huang
ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems. ISCA (2024)
Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES (2023)
Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA (2023)
Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo
Efficient Bad Block Management with Cluster Similarity. HPCA (2022)
Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC (2022)
Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA (2022)
Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21 (3) (2022)
He-Sheng Chou, Hsiang-Yun Cheng, Jun-Xiang Qiu, Tsun-Kuang Chi, Tsung-Yi Chen, Shin-Lun Chen
Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement. ICCE (2022)
Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng
RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment. DATE (2022)
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. ISPASS (2021)
Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo
Future Computing Platform Design: A Cross-Layer Design Approach. DATE (2021)
Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng
RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. DAC (2021)
Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng
ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. ICCD (2021)
Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, Che-Ching Lin
GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. DATE (2020)
Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA (2019)
Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. ICCAD (2019)
Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. IEEE Trans. Computers 68 (12) (2019)
Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD (2018)
Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. CoRR (2018)
Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16 (2) (2017)
Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS (2017)
Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA (2016)
Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. ISCAS (2016)
Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. ACM Trans. Design Autom. Electr. Syst. 21 (1) (2015)
Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin
Core vs. uncore: the heart of darkness. DAC (2015)
Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED (2014)
Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang
Memory Latency Reduction via Thread Throttling. MICRO (2010)