Chung-Hsiang Lin

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 1

Top Topics

Error Correction

Top Venues

ACM Trans. Archit. Code Optim.

Publications

Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC (2022)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD (2012)
Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang
Memory Latency Reduction via Thread Throttling. MICRO (2010)
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. ISLPED (2009)
Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King
Hierarchical value cache encoding for off-chip data bus. ISLPED (2006)