Yi-Jung Chen

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 8

Top Topics

Distributed Memory

Error Correction

Top Venues

Publications

Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA (2023)
Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang
PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. ASP-DAC (2022)
Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. SAC (2020)
Chia-Yin Liu, Cheng-En Wu, Yi-Jung Chen
Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories. RACS (2018)
Che-Wei Chang, Geng-You Chen, Yi-Jung Chen, Chia-Wei Yeh, Pei Yin Eng, Ana Cheung, Chia-Lin Yang
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives. IEEE Trans. Computers 66 (8) (2017)
Yi-Jung Chen, Wen-Wei Chang, Chia-Yin Liu, Cheng-En Wu, Bo-Yuan Chen, Ming-Ying Tsai
Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture. IEEE Access 5 (2017)
Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS (2015)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. ACM Trans. Archit. Code Optim. 12 (2) (2015)
Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang
Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs. DATE (2014)
Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED (2013)
Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang
SECRET: Selective error correction for refresh energy reduction in DRAMs. ICCD (2012)
Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen
Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. ICCAD (2012)
Yi-Jung Chen, Chia-Lin Yang, Jaw-Wei Chi, Jian-Jia Chen
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. IEEE Trans. Computers 60 (6) (2011)
Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE (2010)
Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. J. Syst. Archit. 55 (5-6) (2009)
Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang Sam Han
Improved Modulo (2n+1) Multiplier for IDEA. J. Inf. Sci. Eng. 23 (3) (2007)
Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su
An architectural co-synthesis algorithm for energy-aware network-on-chip design. SAC (2007)
Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen
Cache leakage control mechanism for hard real-time systems. CASES (2007)
Chia-Lin Yang, Shun-Ying Wang, Yi-Jung Chen
Branch Behavior Characterization for Multimedia Applications. Asia-Pacific Computer Systems Architecture Conference (2006)
Yi-Jung Chen, Dyi-Rong Duh, Yunghsiang S. Han
+1) Multiplier for IDEA. Security and Management (2004)