Yi-Chang Lu

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 41

Top Topics

Hardware Implementation

Top Venues

Publications

Hung-Yu Shu, Yi-Hsien Lin, Yi-Chang Lu
Deep Plug-and-play Nighttime Non-blind Deblurring with Saturated Pixel Handling Schemes. WACV (2024)
Hao-Wei Liu, Zhe-Wei Shen, Yang-Ming Yeh, Yi-Chang Lu
A Nucleotide-Position-Based Data Format for Fast Variant Calling and Its Hardware Analyzer Design. BioCAS (2022)
Shih-Shiuan Weng, Yang-Ming Yeh, Yu-Cheng Li, Yi-Chang Lu
An Alignment-Based Hardware Accelerator for Rapid Prediction of RNA Secondary Structures. ISCAS (2022)
Chuan-Yu Chen, Shih-Hao Huang, Yi-Chang Lu
A Hardware Accelerator for Long Sequence Alignment with the Bit-Vector Scoring Scheme and Divide-and-Conquer Traceback. BioCAS (2022)
Chih-Hsiang Yang, Yi-Hsien Lin, Yi-Chang Lu
A Variation-Based Nighttime Image Dehazing Flow With a Physically Valid Illumination Estimator and a Luminance-Guided Coloring Model. IEEE Access 10 (2022)
Bo-Fan Chen, Yang-Ming Yeh, Yi-Chang Lu
CF-Net: Complementary Fusion Network for Rotation Invariant Point Cloud Completion. ICASSP (2022)
Shih-Wei Hsieh, Chih-Hsiang Yang, Yi-Chang Lu
Shadow Removal Through Learning-Based Region Matching and Mapping Function Optimization. ICME (2022)
Yi-Hsien Lin, Yi-Chang Lu
Low-Light Enhancement Using a Plug-and-Play Retinex Model With Shrinkage Mapping for Illumination Estimation. IEEE Trans. Image Process. 31 (2022)
Yang-Ming Yeh, Yi-Chang Lu
MSRCall: a multi-scale deep neural network to basecall Oxford Nanopore sequences. Bioinform. 38 (16) (2022)
Yen-Po Lin, Yang-Ming Yeh, Yu-Chen Chou, Yi-Chang Lu
Attention EdgeConv For 3D Point Cloud Classification. APSIPA ASC (2021)
Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. CoRR (2021)
Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. DATE (2021)
Jing-Ping Wu, Yi-Chien Lin, Ying-Wei Wu, Shih-Wei Hsieh, Ching-Hsuan Tai, Yi-Chang Lu
A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. ISCAS (2021)
Yu-Chen Chou, Yen-Po Lin, Yang-Ming Yeh, Yi-Chang Lu
3D-GFE: a Three-Dimensional Geometric-Feature Extractor for Point Cloud Data. APSIPA ASC (2021)
Fang-Tsung Hsiao, Yi-Hsien Lin, Yi-Chang Lu
Using Regularity Unit As Guidance For Summarization-Based Image Resizing. VCIP (2021)
Sheng-Jui Huang, Yi-Hsien Lin, Chi-Hung Weng, Yi-Chang Lu
A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping. APCCAS (2021)
Yu-Cheng Li, Mao-Jan Lin, Xiao-Xuan Huang, Chien-Yu Chen, Yi-Chang Lu
Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions. BIBE (2020)
Cheng-Yeh Liou, Cheng-Yen Chuang, Chia-Han Huang, Yi-Chang Lu
HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain. VCIP (2020)
Chi-Yun Yang, Yang-Ming Yeh, Yi-Chang Lu
Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data. VLSI-DAT (2020)
Chia-Han Huang, Yi-Chang Lu
An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior. ISCAS (2020)
Yu-Cheng Li, Yi-Chang Lu
BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment. IEEE Trans. Biomed. Circuits Syst. 13 (6) (2019)
Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks. BioCAS (2019)
Man-Rong Chen, Hao-Wei Liu, Yi-Hsien Lin, Yi-Chang Lu
A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data. ISCAS (2019)
Ching-Fan Chiang, Yang-Ming Yeh, Chi-Yun Yang, Yi-Chang Lu
Colorization of High-Frame-Rate Monochrome Videos Using Synchronized Low-Frame-Rate Color Data. CCIW (2019)
Ming-Hung Chen, Mao-Jan Lin, Yu-Cheng Li, Yi-Chang Lu
Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design. BIBE (2019)
Chien-An Wang, Sheng-Jui Huang, Yu-Cheng Li, Yi-Chang Lu
An FPGA-Based Liquid Association Calculator for Genome-Wide Co-Expression Analysis. DSL (2018)
Ruei-Ting Chien, Yi-Lun Liao, Chien-An Wang, Yu-Cheng Li, Yi-Chang Lu
Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment. NORCAS (2018)
Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. ISCAS (2018)
Yi-Lun Liao, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator. ASAP (2018)
Po-Hsiang Hsu, Yang-Ming Yeh, Chi-Ming Yeh, Yi-Chang Lu
A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. ISCAS (2018)
Shih-Wei Hsieh, Yao-Cheng Yang, Chi-Ming Yeh, Sheng-Jui Huang, Yi-Chang Lu
Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. ICIP (2018)
Mao-Jan Lin, Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. ISCAS (2018)
Ya-Fang Shih, Yang-Ming Yeh, Yen-Yu Lin, Ming-Fang Weng, Yi-Chang Lu, Yung-Yu Chuang
Deep Co-occurrence Feature Learning for Visual Object Recognition. CVPR (2017)
Yang-Ming Yeh, Chi-Ming Yeh, Ying-Yu Tseng, Yi-Chang Lu
An orthogonal matching pursuit processor for sparse-representation-based light field data compression. GCCE (2016)
Chun-Shen Liu, Nae-Chyun Chen, Yu-Cheng Li, Yi-Chang Lu
An FPGA-based quality filter for de novo sequence assembly pipeline. APCCAS (2016)
Yu-Hsiang Kao, Sheng-Jui Huang, Yi-Chang Lu
An iterative re-weighted least squares processor design for deblurring parabolic camera images. GCCE (2016)
Chih-Yu Chang, Yu-Cheng Li, Nae-Chyun Chen, Xiao-Xuan Huang, Yi-Chang Lu
A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit method. NORCAS (2016)
Yi-Hsiang Chen, Nae-Chyun Chen, Yu-Hsiang Kao, Yu-Cheng Li, Yi-Chang Lu
Queue-based segmentation algorithm for refining depth maps in light field camera applications. GCCE (2016)
Che-Wei Chang, Min-Hung Chen, Kuan-Chang Chen, Chi-Ming Yeh, Yi-Chang Lu
Mask design for pinhole-array-based hand-held light field cameras with applications in depth estimation. APSIPA (2016)
Xiao-Xuan Huang, Chun-Hsien Ho, Yu-Cheng Li, Nae-Chyun Chen, Yi-Chang Lu
Step shift: A fast image segmentation algorithm and its hardware implementation for next-generation sequencing fluorescence data. APCCAS (2016)
Lu Xiao, Xiao-Xuan Huang, Yi-Chang Lu
Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation. ISOCC (2016)
Yi-Jung Chen, Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu
Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. RACS (2015)
Nae-Chyun Chen, Tai-Yin Chiu, Yu-Cheng Li, Yu-Chun Chien, Yi-Chang Lu
Power efficient special processor design for burrows-wheeler-transform-based short read sequence alignment. BioCAS (2015)
Che-Wei Chang, Man-Rong Chen, Po-Hsiang Hsu, Yi-Chang Lu
A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data. ISCAS (2014)
Chun-Yi Kuo, Chi-Jih Shih, Yi-Chang Lu, James Chien-Mo Li, Krishnendu Chakrabarty
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Min-Hung Chen, Ching-Fan Chiang, Yi-Chang Lu
Depth estimation for hand-held light field cameras under low light conditions. IC3D (2014)
Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu
Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. ISLPED (2013)
Chi-Jih Shih, Shih-An Hsieh, Yi-Chang Lu, James Chien-Mo Li, Tzong-Lin Wu, Krishnendu Chakrabarty
Test Generation of Path Delay Faults Induced by Defects in Power TSV. Asian Test Symposium (2013)
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
Thermal coupling aware task migration using neighboring core search for many-core systems. VLSI-DAT (2013)
Chun-Liang Kuo, Yang-Yao Lin, Yi-Chang Lu
Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data. SoCC (2013)
Chin-Khai Tang, Yi-Chang Lu
A power-efficient asynchronous circuit style with selective input-channel restoring. MWSCAS (2013)
Chin-Khai Tang, Ming-Shing Su, Yi-Chang Lu
LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems. IEEE Signal Process. Lett. 20 (7) (2013)
Chi-Kai Shen, Yi-Chang Lu, Yih-Peng Chiou, Tai-Yu Cheng, Tzong-Lin Wu
Power distribution network modeling for 3-D ICs with TSV arrays. ASP-DAC (2013)
Yuan-Hsiang Kuo, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. ICASSP (2013)
Shih-Chieh Fan Chiang, Po-Hsiang Hsu, Yi-Chang Lu
Light field data processor design for depth estimation using confidence-assisted disparities. SoCC (2013)
Yu-Long Huang, Chun-Shen Liu, Yu-Cheng Li, Yi-Chang Lu
Architecture and circuit design of parallel processing elements for de novo sequence assembly. SoCC (2013)
Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (9) (2011)
Chih-Chieh Chen, Yi-Chang Lu, Ming-Shing Su
Light field based digital refocusing using a DSLR camera with a pinhole array mask. ICASSP (2010)
Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. ASP-DAC (2010)
Yong-Ruei Huang, Jia-Hong Pan, Yi-Chang Lu
Thermal-aware router-sharing architecture for 3D Network-on-Chip designs. APCCAS (2010)
Chih-Chieh Chen, Shih-Chieh Fan Chiang, Xiao-Xuan Huang, Ming-Shing Su, Yi-Chang Lu
Depth estimation of light field data from pinhole-masked DSLR cameras. ICIP (2010)
Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu
Thermal modeling for 3D-ICs with integrated microchannel cooling. ICCAD (2009)
Kuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. ICCAD (2008)
Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu
An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. ISQED (2008)
Cosmin Iorga, Yi-Chang Lu, Robert W. Dutton
A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications. IEEE Trans. Instrum. Meas. 56 (6) (2007)
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong
Performance Benefits of Monolithically Stacked 3-D FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong
Performance benefits of monolithically stacked 3D-FPGA. FPGA (2006)
Georgios Veronis, Yi-Chang Lu, Robert W. Dutton
Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. ISQED (2004)
Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi
Min/max On-Chip Inductance Models and Delay Metrics. DAC (2001)
Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC (2001)