Kaustav Banerjee

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 2

Top Topics

Guided Exploration

Air Conditioning

Engineering Problems

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ankit Kumar, Arnab Pal, Kamyar Parto, Wei Cao, Kaustav Banerjee
Exploration and Exploitation of Strain Engineering in 2D-FETs. DRC (2023)
Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee
Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (7) (2013)
Wei Cao, Jiahao Kang, Wei Liu, Yasin Khatami, Deblina Sarkar, Kaustav Banerjee
2D electronics: Graphene and beyond. ESSDERC (2013)
Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (11) (2012)
Hong Li, Chuan Xu, Kaustav Banerjee
Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs. IEEE Des. Test Comput. 27 (4) (2010)
Hamed F. Dadgour, Muhammad M. Hussain, Casey Smith, Kaustav Banerjee
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. DAC (2010)
Hamed F. Dadgour, Kaustav Banerjee
Aging-resilient design of pipelined architectures using novel detection and correction circuits. DATE (2010)
Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee
Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design. ICCAD (2010)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE (2010)
Hamed F. Dadgour, Kaustav Banerjee
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates. IEEE Trans. Very Large Scale Integr. Syst. 18 (11) (2010)
Hamed F. Dadgour, Muhammad M. Hussain, Kaustav Banerjee
A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. ISLPED (2010)
Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Hamed F. Dadgour, Kaustav Banerjee
Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs. IET Comput. Digit. Tech. 3 (6) (2009)
Kaustav Banerjee
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. SLIP (2009)
Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
CMOS vs Nano: comrades or rivals? FPGA (2009)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009)
Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee
High-speed low-power FinFET based domino logic. ASP-DAC (2009)
Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee
Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. ICCAD (2009)
Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard Smith, Kaustav Banerjee
Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. ICCAD (2009)
Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli
Graphene based transistors: physics, status and future perspectives. ISPD (2009)
Sheng-Chih Lin, Kaustav Banerjee
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Hamed F. Dadgour, Vivek De, Kaustav Banerjee
Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD (2008)
Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. DAC (2008)
Navin Srivastava, Roberto Suaya, Kaustav Banerjee
High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE (2008)
Hamed F. Dadgour, Kaustav Banerjee
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. DAC (2007)
Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design (2007)
Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
3D Integration for Introspection. IEEE Micro 27 (1) (2007)
Sheng-Chih Lin, Kaustav Banerjee
An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. ICCAD (2006)
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC (2006)
Rajiv V. Joshi, Kaustav Banerjee, André DeHon
Tutorial 1: Emerging Technologies for VLSI Design. ISQED (2006)
Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC (2006)
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC (2006)
Kaustav Banerjee, Sungjun Im, Navin Srivastava
Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? Nano-Net (2006)
Kaustav Banerjee, Navin Srivastava
Are carbon nanotubes the future of VLSI interconnections? DAC (2006)
Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
Introspective 3D chips. ASPLOS (2006)
Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
Supply and power optimization in leakage-dominant technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Navin Srivastava, Kaustav Banerjee
Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD (2005)
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (6) (2005)
Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED (2005)
Vineet Wason, Kaustav Banerjee
A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED (2005)
Lech Józwiak, Kaustav Banerjee
Plenary Session 2P. ISQED (2005)
Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD (2005)
Adil Koukab, Kaustav Banerjee, Michel J. Declercq
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. ISQED (2004)
Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . ISQED (2004)
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC (2004)
Songqing Zhang, Vineet Wason, Kaustav Banerjee
A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED (2004)
Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu
Nano, quantum, and molecular computing: are we ready for the validation and test challenges? HLDVT (2003)
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD (2003)
Kaustav Banerjee, Amit Mehrotra
Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (8) (2002)
Kaustav Banerjee, Amit Mehrotra
Inductance Aware Interconnect Scaling. ISQED (2002)
Adil Koukab, Kaustav Banerjee, Michel J. Declercq
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. ICCAD (2002)
Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC (2002)
Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
A SET quantizer circuit aiming at digital communication system. ISCAS (5) (2002)
Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. ISQED (2002)
Kaustav Banerjee, Amit Mehrotra
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. DAC (2001)
Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, Krishna C. Saraswat
3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89 (5) (2001)
Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
Analysis and optimization of thermal issues in high-performance VLSI. ISPD (2001)
Choshu Ito, Kaustav Banerjee, Robert W. Dutton
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. ISQED (2001)
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. DAC (2001)
TingYen Chiang, Kaustav Banerjee, Krishna Saraswat
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. ICCAD (2001)
Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC (2001)
Kaustav Banerjee, Amit Mehrotra
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. ICCAD (2001)
Amir H. Ajami, Massoud Pedram, Kaustav Banerjee
Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs. CICC (2001)
Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. ICCAD (2001)
Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl
Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE 89 (3) (2001)
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat
Multiple Si layer ICs: motivation, performance analysis, and design implications. DAC (2000)
Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur
Performance analysis and technology of 3-D ICs. SLIP (2000)
Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu
On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC (1999)