Kanishka Lahiri

Publication Activity (10 Years)

Years Active: 1999-2020
Publications (10 Years): 5

Top Topics

Radon Transform

Decision Tree Algorithm

Feature Construction

Sampling Strategy

Top Venues

Publications

Sriyash Caculo, Kanishka Lahiri, Subramaniam Kalambur
Characterizing the Scale-Up Performance of Microservices using TeaStore. IISWC (2020)
Disha Talreja, Kanishka Lahiri, Subramaniam Kalambur, Prakash Raghavendra
Performance Scaling of Cassandra on High-Thread Count Servers. ICPE (2019)
Rajesh Kumar, Suchita Pati, Kanishka Lahiri
DARTS: Performance-counter driven sampling using binary translators. ISPASS (2017)
Kanishka Lahiri, Subhash Kunnoth
Fast IPC estimation for performance projections using proxy suites and decision trees. ISPASS (2017)
Srividya Ramanathan, Gautam Hazari, Kanishka Lahiri, Francesco Spadini
Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory. HiPC (2015)
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Variation-Aware System-Level Power Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Variation-Tolerant Dynamic Power Management at the System-Level. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 16 (10) (2008)
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. VLSI Design (2007)
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. DAC (2007)
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
System-on-Chip Power Management Considering Leakage Power Variations. DAC (2007)
Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design (2007)
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE (2006)
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Considering process variations during system-level power analysis. ISLPED (2006)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
The LOTTERYBUS on-chip communication architecture. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
Power analysis of mobile 3D graphics. DATE (2006)
Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan
Adaptive data placement in an embedded multiprocessor thread library. DATE (2006)
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
Signature-based workload estimation for mobile 3D graphics. DAC (2006)
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
SOFTENIT: a methodology for boosting the software content of system-on-chip designs. ACM Great Lakes Symposium on VLSI (2005)
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. VLSI Design (2005)
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC (2005)
Chulsung Park, Kanishka Lahiri, Anand Raghunathan
Battery discharge characteristics of wireless sensor nodes: an experimental analysis. SECON (2005)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Efficient power profiling for battery-driven embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Krishna Sekar, Kanishka Lahiri, Sujit Dey
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. VLSI Design (2004)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Kanishka Lahiri, Anand Raghunathan
Power analysis of system-level on-chip communication architectures. CODES+ISSS (2004)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Design space exploration for optimizing on-chip communication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Krishna Sekar, Kanishka Lahiri, Sujit Dey
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ICCAD (2003)
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
Communication architecture based power management for battery efficient system design. DAC (2002)
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
Communication-Based Power Management. IEEE Des. Test Comput. 19 (4) (2002)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. VLSI Design (2002)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Battery-efficient architecture for an 802.11 MAC processor. ICC (2002)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Fast system-level power profiling for battery-efficient system design. CODES (2002)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (6) (2001)
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design (2001)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. DAC (2001)
Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
Battery Life Estimation of Mobile Embedded Systems. VLSI Design (2001)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD (2000)
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design (2000)
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC (2000)
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD (1999)