Marcello Lajolo

Publication Activity (10 Years)

Years Active: 1998-2008
Publications (10 Years): 0

Publications

Simone Medardoni, Marcello Lajolo, Davide Bertozzi
Variation tolerant NoC design by means of self-calibrating links. DATE (2008)
Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar
In Memoriam: Margarida F. Jacome. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
André C. Nácul, Francesco Regazzoni, Marcello Lajolo
Hardware scheduling support in SMP architectures. DATE (2007)
Subhek Garg, Marcello Lajolo
C-based Design of a Flexible Wrapper for Tiled Networks On Chip. FDL (2006)
Sathish Chandra, Francesco Regazzoni, Marcello Lajolo
Hardware/software partitioning of operating systems: a behavioral synthesis approach. ACM Great Lakes Symposium on VLSI (2006)
André C. Nácul, Marcello Lajolo, T. Givarjis
Interface-Centric Abstraction Level for Rapid HW/SW Integration. FDL (2005)
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
SOFTENIT: a methodology for boosting the software content of system-on-chip designs. ACM Great Lakes Symposium on VLSI (2005)
Francesco Regazzoni, André C. Nácul, Marcello Lajolo
Automatic synthesis of the Hardware/Software Interface. FDL (2005)
Chen He, Marcello Lajolo, Margarida F. Jacome
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. PDP (2003)
Dirceu Cavendish, Marcello Lajolo, Hongbo Liu
On the evaluation of fairness for input queue switches. ICC (2002)
Dirceu Cavendish, Marcello Lajolo, Hongbo Liu
On the support of minimum service rates for input queue switches. ICC (2002)
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
Cosimulation-based power estimation for system-on-chip design. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Marcello Lajolo
Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 9 (6) (2001)
Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design (2001)
Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
Automatic test bench generation for simulation-based validation. CODES (2000)
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
Early Power Estimation for System-on-Chip Designs. PATMOS (2000)
Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
Behavioral-level test vector generation for system-on-chip designs. HLDVT (2000)
Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
System-level test bench generation in a co-design framework. ETW (2000)
Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
Evaluating System Dependability in a Co-Design Framework. DATE (2000)
Mihai T. Lazarescu, Jwahar R. Bammi, Edwin A. Harcourt, Luciano Lavagno, Marcello Lajolo
Compilation-based software performance estimation for system level design. HLDVT (2000)
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE (2000)
Marcello Lajolo, Mihai T. Lazarescu, Alberto L. Sangiovanni-Vincentelli
A compilation-based software estimation scheme for hardware/software co-simulation. CODES (1999)
Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. ASP-DAC (1999)
Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli
Software timing analysis using HW/SW cosimulation and instruction set simulator. CODES (1998)
Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES (1998)