Sachin S. Sapatnekar

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 146

Top Venues

Publications

Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar
IR-Aware ECO Timing Optimization Using Reinforcement Learning. CoRR (2024)
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Rongjian Liang, Haoxing Ren, Sachin S. Sapatnekar, Bing-Yue Wu
OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education. VTS (2024)
Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
On Error Correction for Nonvolatile Processing-In-Memory. ISCA (2024)
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC (2024)
Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC (2024)
Chetan Choppali Sudarshan, Nikhil Matkar, Sarma B. K. Vrudhula, Sachin S. Sapatnekar, Vidya A. Chhabria
ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSI. HPCA (2024)
Shiyu Guo, Sachin S. Sapatnekar, Jie Gu
2.5 A 28nm Physical-Based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices. ISSCC (2024)
Zamshed I. Chowdhury, Hüsrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
On Gate Flip Errors in Computing-In-Memory. DATE (2024)
Vidya A. Chhabria, Chetan Choppali Sudarshan, Sarma Vrudhula, Sachin S. Sapatnekar
Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems. CoRR (2023)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
M. Hüsrev Cilasun, Ziqing Zeng, Ramprasath S, Abhimanyu Kumar, Hao Lo, William Cho, Chris H. Kim, Ulya R. Karpuzcu, Sachin S. Sapatnekar
3SAT on an All-to-All-Connected CMOS Ising Solver Chip. CoRR (2023)
Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Ziqing Zeng, Sachin S. Sapatnekar
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations. CoRR (2023)
Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Nestor E. Evmorfopoulos, Mohammad Abdullah Al Shohel, Olympia Axelou, Pavlos Stoikos, Vidya A. Chhabria, Sachin S. Sapatnekar
Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects. ISPD (2023)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. ACM Trans. Design Autom. Electr. Syst. 28 (1) (2023)
Salonik Resch, Hüsrev Cilasun, Masoud Zabihi, Zamshed Iqbal Chowdhury, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
PimCity: A Compute in Memory Substrate featuring both Row and Column Parallel Computing. ICRC (2023)
Vidya A. Chhabria, Sachin S. Sapatnekar
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design. ISQED (2023)
Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestoras E. Evmorfopoulos, Sachin S. Sapatnekar
Frequency-Domain Transient Electromigration Analysis Using Circuit Theory. ICCAD (2023)
Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE (2023)
Yang Lv, Brandon R. Zink, Robert P. Bloom, M. Hüsrev Cilasun, Pravin Khanal, Salonik Resch, Zamshed I. Chowdhury, Ali Habiboglu, Weigang Wang, Sachin S. Sapatnekar, Ulya R. Karpuczu, Jianping Wang
Experimental demonstration of magnetic tunnel junction-based computational random-access memory. CoRR (2023)
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. CoRR (2023)
Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. ASP-DAC (2023)
Sudipta Mondal, Ramprasath S, Ziqing Zeng, Kishor Kunal, Sachin S. Sapatnekar
A Multicore GNN Training Accelerator. ISLPED (2023)
Ziqing Zeng, Sachin S. Sapatnekar
Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications. DATE (2023)
Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE (2023)
Sachin S. Sapatnekar
The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues. ISPD (2023)
Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC (2023)
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators. CoRR (2023)
Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
On Endurance of Processing in (Nonvolatile) Memory. ISCA (2023)
Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD (2023)
Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar
GNNIE: GNN inference engine with load-balancing and graph-specific caching. DAC (2022)
Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Are Analytical Techniques Worthwhile for Analog IC Placement? DATE (2022)
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Yang Lv, Brandon Zink, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Error Detection and Correction for Processing in Memory (PiM). CoRR (2022)
Sachin S. Sapatnekar
EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine Learning. IPDPS Workshops (2022)
Zamshed I. Chowdhury, S. Karen Khatamifard, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Meisam Razaviyayn, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC (2022)
Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George Stamoulis, Sachin S. Sapatnekar
A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. ICCAD (2022)
Vidya A. Chhabria, Sachin S. Sapatnekar
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (10) (2022)
Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE (2022)
Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions. ACM Trans. Embed. Comput. Syst. 21 (5) (2022)
Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction. MLCAD (2022)
Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD (2022)
Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE (2022)
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms. MLCAD (2022)
Hadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis. ICCAD (2021)
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. CoRR (2021)
Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. DATE (2021)
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects. CoRR (2021)
Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Sachin S. Sapatnekar
GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Caching. CoRR (2021)
Zamshed I. Chowdhury, Salonik Resch, M. Hüsrev Cilasun, Zhengyang Zhao, Masoud Zabihi, Sachin S. Sapatnekar, Jianping Wang, Ulya R. Karpuzcu
CAMeleon: Reconfigurable B(T)CAM in Computational RAM. ACM Great Lakes Symposium on VLSI (2021)
Susmita Dey Manasi, Sachin S. Sapatnekar
DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators. ASP-DAC (2021)
Salonik Resch, Zamshed I. Chowdhury, M. Hüsrev Cilasun, Masoud Zabihi, Zhengyang Zhao, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Towards Homomorphic Inference Beyond the Edge. CoRR (2021)
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Spiking Neural Networks in Spintronic Computational RAM. ACM Trans. Archit. Code Optim. 18 (4) (2021)
Luke R. Everson, Sachin S. Sapatnekar, Chris H. Kim
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control. IEEE J. Solid State Circuits 56 (7) (2021)
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Sachin S. Sapatnekar
A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects. DAC (2021)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. CoRR (2021)
Masoud Zabihi, Salonik Resch, M. Hüsrev Cilasun, Zamshed I. Chowdhury, Zhengyang Zhao, Ulya R. Karpuzcu, Jianping Wang, Sachin S. Sapatnekar
Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator. CoRR (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38 (2) (2021)
Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani
Analog Layout Generation using Optimized Primitives. DATE (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD (2021)
Farhana Sharmin Snigdha, Susmita Dey Manasi, Jiang Hu, Sachin S. Sapatnekar
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (7) (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
Machine Learning Techniques in Analog Layout Automation. ISPD (2021)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD (2021)
Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD (2021)
Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE (2021)
Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar
BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology. ICCAD (2021)
Vidya A. Chhabria, Sachin S. Sapatnekar
OpeNPDN: A Neural-network-based Framework for Power Delivery Network Synthesis. CoRR (2021)
Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar
Aging of Current DACs and its Impact in Equalizer Circuits. IRPS (2021)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. ASP-DAC (2021)
Mohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar
Analytical Modeling of Transient Electromigration Stress based on Boundary Reflections. ICCAD (2021)
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jian-Ping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM. SEED (2021)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD (2020)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD (2020)
Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
PIMBALL: Binary Neural Networks in Spintronic Memory. ACM Trans. Archit. Code Optim. 16 (4) (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD (2020)
Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
Learning from Experience: Applying ML to Analog Circuit Design. ISPD (2020)
M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. DAC (2020)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE (2020)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR (2020)
M. Hüsrev Cilasun, Salonik Resch, Zamshed I. Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Keshab K. Parhi, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM). CoRR (2020)
Salonik Resch, S. Karen Khatamifard, Zamshed I. Chowdhury, Masoud Zabihi, Zhengyang Zhao, M. Hüsrev Cilasun, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
MOUSE: Inference In Non-volatile Memory for Energy Harvesting Applications. MICRO (2020)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. CoRR (2020)
Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar
MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification. CoRR (2020)
Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. IEEE Trans. Very Large Scale Integr. Syst. 28 (8) (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
ALIGN: A System for Automating Analog Layout. CoRR (2020)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI (2020)
Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, Bangqi Xu
Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques. ASP-DAC (2020)
Qianqian Fan, David J. Lilja, Sachin S. Sapatnekar
Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage. IEEE Trans. Computers 69 (2) (2020)
Tengtao Li, Sachin S. Sapatnekar
Stress-Induced Performance Shifts in Flexible System-in-Foils Using Ultra-Thin Chips. ISQED (2020)
Chaofan Li, Sachin S. Sapatnekar, Jiang Hu
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. ISQED (2019)
Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar
SeFAct: selective feature activation and early classification for CNNs. ASP-DAC (2019)
Tengtao Li, Sachin S. Sapatnekar
Stress-Induced Performance Shifts in 3D DRAMs. ACM Trans. Design Autom. Electr. Syst. 24 (5) (2019)
Lin Huang, I-Hong Hou, Sachin S. Sapatnekar, Jiang Hu
Improving QoS for Global Dual-Criticality Scheduling on Multiprocessors. RTCSA (2019)
Sachin S. Sapatnekar
Electromigration-Aware Interconnect Design. ISPD (2019)
Salonik Resch, S. Karen Khatamifard, Zamshed Iqbal Chowdhury, Masoud Zabihi, Zhengyang Zhao, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu
A Machine Learning Accelerator In-Memory for Energy Harvesting. CoRR (2019)

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Publication Activity (10 Years)

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Sachin S. Sapatnekar