Tonmoy Dhar

Publication Activity (10 Years)

Years Active: 2017-2023
Publications (10 Years): 14

Top Topics

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Reliability Analysis

Machine Learning Models

Top Venues

Publications

Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE (2022)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38 (2) (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
Machine Learning Techniques in Analog Layout Automation. ISPD (2021)
Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC (2021)
Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar
Aging of Current DACs and its Impact in Equalizer Circuits. IRPS (2021)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD (2020)
Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
Learning from Experience: Applying ML to Analog Circuit Design. ISPD (2020)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE (2020)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
ALIGN: A System for Automating Analog Layout. CoRR (2020)
Tonmoy Dhar, Sachin S. Sapatnekar
Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation. IRPS (2019)
Tonmoy Dhar, Swarup Bhunia, Amit Ranjan Trivedi
A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES. MWSCAS (2017)