Ramesh Harjani

ORCID

Publication Activity (10 Years)

Years Active: 1987-2024
Publications (10 Years): 65

Top Venues

CICC

DATE

ICCAD

IEEE J. Solid State Circuits

Publications

Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar
Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC (2024)
Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC (2024)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun
AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE (2023)
Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE (2023)
Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani
Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC (2023)
Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD (2023)
Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Are Analytical Techniques Worthwhile for Analog IC Placement? DATE (2022)
Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC (2022)
Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE (2022)
Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD (2022)
Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE (2022)
Sanggeun Lee, Ramesh Harjani, Taehyoun Oh
Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Taehyoun Oh, Joonho Gil, Ramesh Harjani
Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Jitesh Poojary, Ramesh Harjani
6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB. ISSCC (2021)
Ramesh Harjani, Mike Chen, Marco Berkhout, Johan H. C. van den Heuvel, Thomas H. Lee, Robert Bogdan Staszewski, Kathleen Philips, Howard C. Luong, Vadim Ivanov
SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers. ISSCC (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
ALIGN: A System for Automating Analog Layout. IEEE Des. Test 38 (2) (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD (2021)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
Machine Learning Techniques in Analog Layout Automation. ISPD (2021)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD (2021)
Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD (2021)
Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC (2021)
Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE (2021)
Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar
Aging of Current DACs and its Impact in Equalizer Circuits. IRPS (2021)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD (2020)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD (2020)
Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
Learning from Experience: Applying ML to Analog Circuit Design. ISPD (2020)
Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE (2020)
Shiva Jamali-Zavareh, Ramesh Harjani
Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR (2020)
Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
ALIGN: A System for Automating Analog Layout. CoRR (2020)
Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI (2020)
Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani
Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. MWSCAS (2019)
Saurabh Chaubey, Ramesh Harjani
A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS. CICC (2019)
Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC (2019)
Naser Mousavi, Zhiheng Wang, Danijela Cabric, Ramesh Harjani
A 0.4-1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection. IEEE J. Solid State Circuits 54 (7) (2019)
Anindya Saha, Saurabh Chaubey, Ramesh Harjani
A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications. MWSCAS (2018)
Xingyi Hua, Ramesh Harjani
A 5μW-5mW input power range, 0-3.5V output voltage range RF energy harvester with power-estimator-enhanced MPPT controller. CICC (2018)
Mustafijur Rahman, Ramesh Harjani
A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards. ICECS (2018)
Qingrui Meng, Ramesh Harjani
A 4GHz Instantaneous Bandwidth Low Squint Phased Array Using Sub-Harmonic ILO Based Channelization. ESSCIRC (2018)
Mustafijur Rahman, Ramesh Harjani
A 2.4-GHz, Sub-1-V, 2.8-dB NF, 475-µW Dual-Path Noise and Nonlinearity Cancelling LNA for Ultra-Low-Power Radios. IEEE J. Solid State Circuits 53 (5) (2018)
Naser Mousavi, Zhiheng Wang, Ramesh Harjani
A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. ESSCIRC (2018)
Saurabh Chaubey, Ramesh Harjani
Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges. CICC (2017)
Hundo Shin, Ramesh Harjani
Low-Power Wideband Analog Channelization Filter Bank Using Passive Polyphase-FFT Techniques. IEEE J. Solid State Circuits 52 (7) (2017)
Saurabh Chaubey, Ramesh Harjani
A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency. A-SSCC (2017)
M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
An Overview of Time-Based Computing with Stochastic Constructs. IEEE Micro 37 (6) (2017)
M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Ramesh Harjani
Integrated DC-DC converter design. CICC (2017)
Qingrui Meng, Ramesh Harjani
An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm. ESSCIRC (2016)
Hundo Shin, Ramesh Harjani
A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank. ESSCIRC (2016)
Shiva Jamali-Zavareh, Ramesh Harjani
A jitter-resilient sampling technique for high-resolution ADCs in wideband RF receivers. ICECS (2016)
Mustafijur Rahman, Ramesh Harjani
CMOS energy efficient integrated radios for emerging low power standards. ISOCC (2016)
Rakesh Kumar Palani, Ramesh Harjani
A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm. CICC (2015)
Mustafijur Rahman, Mohammad Elbadry, Ramesh Harjani
An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking. IEEE J. Solid State Circuits 50 (5) (2015)
Ramesh Harjani, Rakesh Kumar Palani
Design of PVT tolerant inverter based circuits for low supply voltages. CICC (2015)
Rakesh Kumar Palani, Ramesh Harjani
A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (11) (2015)
Ramesh Harjani, Danijela Cabric, Dejan Markovic, Brian M. Sadler, Rakesh Kumar Palani, Anindya Saha, Hundo Shin, Eric Rebeiz, Sina Basir-Kazeruni, Fang-Li Yuan
Wideband blind signal classification on a battery budget. IEEE Commun. Mag. 53 (10) (2015)
Fang-Li Yuan, Rakesh Kumar Palani, Sina Basir-Kazeruni, Hundo Shin, Anindya Saha, Ramesh Harjani, Dejan Markovic
A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. VLSIC (2015)
Xingyi Hua, Ramesh Harjani
3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%. CICC (2015)
Rakesh Kumar Palani, Aravindhan Rangarajan, Ramesh Harjani
Chopper stabilized sub 1V reference voltage in 65nm CMOS. MWSCAS (2015)
Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic, Ramesh Harjani
An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS. CICC (2015)
Mohammad Elbadry, Sachin Kalia, Ramesh Harjani
A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz. CICC (2014)
Rakesh Kumar Palani, Ramesh Harjani
High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. CICC (2014)
Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani
High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. CICC (2014)
Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, Ramesh Harjani
Building an on-chip spectrum sensor for cognitive radios. IEEE Commun. Mag. 52 (4) (2014)
Ramesh Harjani, Saurabh Chaubey
A unified framework for capacitive series-parallel DC-DC converter design. CICC (2014)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48 (6) (2013)
Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, Ramesh Harjani
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. IEEE J. Solid State Circuits 48 (5) (2013)
Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2013)
Sudhir S. Kudva, Ramesh Harjani
Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. IEEE J. Solid State Circuits 48 (8) (2013)
Taehyoun Oh, Ramesh Harjani
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS. IEEE J. Solid State Circuits 48 (6) (2013)
Sachin Kalia, Satwik A. Patnaik, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry, Ramesh Harjani
Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48 (5) (2013)
Alberto Valdes-Garcia, Ramesh Harjani
Radio receiver techniques. CICC (2012)
Taehyoun Oh, Ramesh Harjani
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS. VLSIC (2012)
Sudhir S. Kudva, Ramesh Harjani
Fully integrated capacitive converter with all digital ripple mitigation. CICC (2012)
Jaehyup Kim, Bruce Hammer, Ramesh Harjani
A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopy. CICC (2012)
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC (2012)
Satwik A. Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry, Ramesh Harjani
An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS. CICC (2012)
Taehyoun Oh, Ramesh Harjani
A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os. IEEE J. Solid State Circuits 46 (8) (2011)
Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani
Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology. IEEE J. Solid State Circuits 46 (9) (2011)
Sudhir S. Kudva, Ramesh Harjani
Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. IEEE J. Solid State Circuits 46 (8) (2011)
Bodhisatwa Sadhu, Ramesh Harjani
Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%). ISCAS (2010)
Sudhir S. Kudva, Ramesh Harjani
Fully integrated on-chip DC-DC converter with a 450x output range. CICC (2010)
Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links. IEEE J. Solid State Circuits 45 (8) (2010)
Taehyoun Oh, Ramesh Harjani
A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. CICC (2010)
Satwik A. Patnaik, Narasimha Lanka, Ramesh Harjani
A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS. ISSCC (2009)
Jie Gu, Ramesh Harjani, Chris H. Kim
Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. IEEE Trans. Very Large Scale Integr. Syst. 17 (2) (2009)
Ramesh Harjani, Alireza Shirvani Marvell
Millimeter-wave ICs. CICC (2009)
Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. CICC (2009)
Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani
A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology. CICC (2009)
Bodhisatwa Sadhu, Jaehyup Kim, Ramesh Harjani
A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO. CICC (2009)
Kin-Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi, Ramesh Harjani
A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator. IEEE Trans. Circuits Syst. II Express Briefs (5) (2008)
Bodhisatwa Sadhu, Umaikhe E. Omole, Ramesh Harjani
Modeling and synthesis of wide-band switched-resonators for VCOs. CICC (2008)
Liuchun Cai, Ramesh Harjani
Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs. CICC (2008)
Mahmoud Reza Ahmadi, Jaekyun Moon, Ramesh Harjani
Constrained Partial Response Receivers for High-Speed Links. IEEE Trans. Circuits Syst. II Express Briefs (10) (2008)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ramesh Harjani