Lawrence T. Pileggi

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 26

Top Venues

CoRR

IEEE Trans. Circuits Syst. I Regul. Pap.

ASP-DAC

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi
Quantifying the Efficacy of Logic Locking Methods. VLSID (2024)
Brian Singer, Amritanshu Pandey, Shimiao Li, Lujo Bauer, Craig Miller, Lawrence T. Pileggi, Vyas Sekar
Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations. SP (2023)
Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno
Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. 2022 (2022)
Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi
Quantifying the Efficacy of Logic Locking Methods. CoRR (2021)
Joseph Sweeney, Samuel Pagliarini, Lawrence T. Pileggi
Securing Digital Systems via Split-Chip Obfuscation. CoRR (2020)
Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi
Latch-Based Logic Locking. CoRR (2020)
Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi
Latch-Based Logic Locking. HOST (2020)
Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi
Modeling Techniques for Logic Locking. CoRR (2020)
Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi
Modeling Techniques for Logic Locking. ICCAD (2020)
Samuel N. Pagliarini, Sudipta Bhuin, Mehmet Meric Isgenc, Ayan Kumar Biswas, Lawrence T. Pileggi
A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 31 (4) (2020)
Joseph Sweeney, Marijn Heule, Lawrence T. Pileggi
Sensitivity Analysis of Locked Circuits. LPAR (2020)
Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi
CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. 5 (55) (2020)
Ioannis Karageorgos, Mehmet Meric Isgenc, Samuel Pagliarini, Lawrence T. Pileggi
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. J. Hardw. Syst. Secur. 3 (4) (2019)
Marko Jereminov, Bryan Hooi, Amritanshu Pandey, Hyun Ah Song, Christos Faloutsos, Lawrence T. Pileggi
Impact of Load Models on Power Flow Optimization. CoRR (2019)
Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Thomas C. Jackson, Samuel Pagliarini, Lawrence T. Pileggi
An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. ICRC (2018)
Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes
Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED (2017)
Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. NANOARCH (2017)
Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. Integr. 52 (2016)
Rongye Shi, Thomas C. Jackson, Brian Swenson, Soummya Kar, Lawrence T. Pileggi
On the design of phase locked loop oscillatory neural networks: Mitigation of transmission delay effects. IJCNN (2016)
Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ASP-DAC (2015)
Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi
Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi
An RRAM-based Oscillatory Neural Network. LASCAS (2015)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Minhee Jun, Rohit Negi, Jun Tao, Ying-Chih Wang, Shihui Yin, Tamal Mukherjee, Xin Li, Lawrence T. Pileggi
Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. MILCOM (2014)
Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi
Toward efficient programming of reconfigurable radio frequency (RF) receivers. ASP-DAC (2014)
Vanessa H.-C. Chen, Lawrence T. Pileggi
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI. IEEE J. Solid State Circuits 49 (12) (2014)
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC (2013)
Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48 (5) (2013)
Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi
Statistical design and optimization for adaptive post-silicon tuning of MEMS filters. DAC (2012)
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC (2012)
Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits 46 (8) (2011)
Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno
Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC (2011)
Alyssa Bonnoit, Lawrence T. Pileggi
Reducing variability in chip-multiprocessors with adaptive body biasing. ISLPED (2010)
Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC (2010)
Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. ISLPED (2009)
Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi
SRAM parametric failure analysis. DAC (2009)
Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
Creating an affordable 22nm node using design-lithography co-optimization. DAC (2009)
Jonathan E. Proesel, Lawrence T. Pileggi
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. CICC (2008)
Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC (2008)
Xin Li, Yaping Zhan, Lawrence T. Pileggi
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96 (2) (2008)
Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (6) (2008)
Jian Wang, Xin Li, Lawrence T. Pileggi
Parameterized Macromodeling for Analog System-Level Design Exploration. DAC (2007)
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction CoRR (2007)
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi
Asymptotic Probability Extraction for Nonnormal Performance Distributions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (1) (2007)
Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD (2007)
Xin Li, Lawrence T. Pileggi
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits. DAC (2007)
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (1) (2007)
Kim Yaw Tong, Lawrence T. Pileggi
Design Methodology of Regular Logic Bricks for Robust Integrated Circuits. ICCD (2006)
Xin Li, Jiayong Le, Lawrence T. Pileggi
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. DAC (2006)
Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Xin Li, Jiayong Le, Lawrence T. Pileggi
Statistical Performance Modeling and Optimization. Found. Trends Electron. Des. Autom. 1 (4) (2006)
Gökçe Keskin, Xin Li, Lawrence T. Pileggi
Active On-Die Suppression of Power Supply Noise. CICC (2006)
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi
Architecture-aware FPGA placement using metric embedding. DAC (2006)
V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
Design methodology for IC manufacturability based on regular logic-bricks. DAC (2005)
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas
Projection-based performance modeling for inter/intra-die variations. ICCAD (2005)
Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE (2005)
Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD (2005)
Rohan Batra, Peng Li, Lawrence T. Pileggi, Wanju Chiang
A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators. CICC (2005)
Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang
Performance-centering optimization for system-level analog design exploration. ICCAD (2005)
Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. DAC (2005)
Xin Li, Peng Li, Lawrence T. Pileggi
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. ICCAD (2005)
Peng Li, Lawrence T. Pileggi
Compact reduced-order modeling of weakly nonlinear analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (2) (2005)
Peng Li, Yangdong Deng, Lawrence T. Pileggi
Temperature-Dependent Optimization of Cache Leakage Power Dissipation. ICCD (2005)
Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma
Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC (2005)
V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi
Routing architecture exploration for regular fabrics. DAC (2004)
Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi
A frequency relaxation approach for analog/RF system-level simulation. DAC (2004)
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
ORACLE: optimization with recourse of analog circuits including layout extraction. DAC (2004)
Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi
Asymptotic probability extraction for non-normal distributions of circuit performance. ICCAD (2004)
Yang Xu, Cameron Boone, Lawrence T. Pileggi
Metal-mask configurable RF front-end circuits. IEEE J. Solid State Circuits 39 (8) (2004)
Jiayong Le, Xin Li, Lawrence T. Pileggi
STAC: statistical timing analysis with correlation. DAC (2004)
Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi
Robust analog/RF circuit design with projection-based posynomial modeling. ICCAD (2004)
Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi
A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD (2004)
Peng Li, Lawrence T. Pileggi
Efficient harmonic balance simulation using multi-level frequency decomposition. ICCAD (2004)
Michael W. Beattie, Lawrence T. Pileggi
Parasitics extraction with multipole refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Satrajit Gupta, Lawrence T. Pileggi
CHIME: coupled hierarchical inductance model evaluation. DAC (2004)
Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi
Exploring Logic Block Granularity for Regular Fabrics. DATE (2004)
Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra
Efficient full-chip thermal modeling and analysis. ICCAD (2004)
Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE (2004)
Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi
An architectural exploration of via patterned gate arrays. ISPD (2003)
Hui Zheng, Byron Krauter, Lawrence T. Pileggi
On-package decoupling optimization with package macromodels. CICC (2003)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, K. Y. Tong
Exploring regular fabrics to optimize the performance-cost trade-off. DAC (2003)
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
Noise Macromodel for Radio Frequency Integrated Circuits. DATE (2003)
Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL (2003)
Hui Zheng, Byron Krauter, Lawrence T. Pileggi
Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Des. Test Comput. 20 (3) (2003)
Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
Heterogeneous Programmable Logic Block Architectures. DATE (2003)
Xin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi
A frequency separation macromodel for system-level simulation of RF circuits. ASP-DAC (2003)
Peng Li, Lawrence T. Pileggi
Efficient per-nonlinearity distortion analysis for analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (10) (2003)
Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi
Fast, cheap and under control: the next implementation fabric. DAC (2003)
K. Y. Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit
Regular logic fabrics for a via patterned gate array (VPGA). CICC (2003)
Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD (2003)
Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. ICCAD (2003)
Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas
Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI (2003)
E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi
Power Comparison of Throughput Optimized IC Busses. ISVLSI (2003)

Lawrence T. Pileggi.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Lawrence T. Pileggi