Mayler G. A. Martins

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 16

Top Topics

Predicate Logic

Timing Constraints

Eliminating Redundant

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Microelectron. Reliab.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (10) (2023)
Zain Ul Abideen, Tiago Diadami Perez, Mayler G. A. Martins, Samuel Pagliarini
A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. CoRR (2022)
Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28 (2) (2020)
Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt
Improving approximate-TMR using multi-objective optimization genetic algorithm. LATS (2018)
Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt
Design of approximate-TMR using approximate library and heuristic approaches. Microelectron. Reliab. (2018)
Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED (2017)
Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS (2015)
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron. Reliab. 55 (9-10) (2015)
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD (2015)
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. LATS (2015)
Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen
Open Cell Library in 15nm FreePDK Technology. ISPD (2015)
Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC (2014)
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
A constructive approach for threshold logic circuit synthesis. ISCAS (2014)
Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW (2014)
Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Read-polarity-once Boolean functions. SBCCI (2013)
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
Spin diode network synthesis using functional composition. SBCCI (2013)
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Synthesis of threshold logic gates to nanoelectronics. SBCCI (2013)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Iterative remapping respecting timing constraints. ISVLSI (2013)
Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Functional composition: A new paradigm for performing logic synthesis. ISQED (2012)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
KL-cut based digital circuit remapping. NORCHIP (2012)
Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI (2011)
Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis
Boolean factoring with multi-objective goals. ICCD (2010)