André Inácio Reis

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 28

Top Venues

SBCCI

ISCAS

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

ISPD

Publications

Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Extending Multilevel ALS to Design ATMRs. LASCAS (2024)
Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis
An Improved method to join BDDs for incompletely specified Boolean functions. ISCAS (2023)
Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
Effect of Unique Table Implementation in the Performance of BDD Packages. SBCCI (2023)
Alcides S. Costa, Leonardo Droves Silveira, André Inácio Reis
Live Demonstration: Pitanga Platform for Virtual FPGA Remote Laboratories. ISCAS (2023)
Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI (2023)
Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
ATMR design by construction based on two-level ALS. SBCCI (2023)
Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
Possible Reductions to Generate circuits from BDDs. ISVLSI (2022)
Alcides S. Costa, Leonardo Droves Silveira, André Inácio Reis
A Virtual Board Approach for Prototyping and Teaching Digital Design. SBCCI (2022)
Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen
Optimizing machine learning logic circuits with constant signal propagation. Integr. 87 (2022)
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (3) (2020)
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37 (3) (2020)
Jody Maick Matos, Jordi Carrabina, André Inácio Reis
Efficiently Mapping VLSI Circuits With Simple Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas
Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (5) (2019)
Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis
Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI (2019)
Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
André Inácio Reis
Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution. ISPD (2018)
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI (2018)
Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
Unlocking fine-grain parallelism for AIG rewriting. ICCAD (2018)
Jody Maick Matos, André Inácio Reis, Jordi Carrabina
Technology Mapping for Circuits with Simple Cells. ISCAS (2018)
Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Simone R. N. Reis, André Inácio Reis, Jordi Carrabina, Pompeu Casanovas
Contributions to Modeling Patent Claims When Representing Patent Knowledge. AICOL (2017)
Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas
Binary adder circuit design using emerging MIGFET devices. ISQED (2017)
Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
Fast-extract with cube hashing. ASP-DAC (2017)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS (2016)
Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. ISPD (2015)
Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
SOP based logic synthesis for memristive IMPLY stateful logic. ICCD (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS (2015)
Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko
Threshold Logic Synthesis Based on Cut Pruning. ICCAD (2015)
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
Exploring the use of approximate TMR to mask transient faults in logic with low area overhead. Microelectron. Reliab. 55 (9-10) (2015)
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD (2015)
Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. LATS (2015)
Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen
Open Cell Library in 15nm FreePDK Technology. ISPD (2015)
Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Fast buffer delay estimation considering time-dependent dielectric breakdown. ISCAS (2015)
Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC (2014)
Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
CMOS inverter analytical delay model considering all operating regions. ISCAS (2014)
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
A constructive approach for threshold logic circuit synthesis. ISCAS (2014)
Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW (2014)
Jody Maick Matos, Marcus Ritt, Renato P. Ribas, André Inácio Reis
Deriving Reduced Transistor Count Circuits from AIGs. SBCCI (2014)
Manuel Llamas, Mohammad Mashayekhi, Jordi Carrabina, Jody Maick Matos, André Inácio Reis
Optimization on cell-library design for digital Application Specific Printed Electronics Circuits. PATMOS (2014)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI (2014)
Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
CMOS inverter delay model based on DC transfer curve for slow input. ISQED (2013)
Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
A methodology to evaluate the aging impact on flip-flops performance. SBCCI (2013)
Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Delay model for static CMOS complex gates. SBCCI (2013)
Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Read-polarity-once Boolean functions. SBCCI (2013)
Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis
Spin diode network synthesis using functional composition. SBCCI (2013)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. 53 (9-11) (2013)
Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53 (9-11) (2013)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI (2013)
Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Synthesis of threshold logic gates to nanoelectronics. SBCCI (2013)
Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis
Logic synthesis for manufacturability considering regularity and lithography printability. ISVLSI (2013)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Transistor-level optimization of CMOS complex gates. LASCAS (2013)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Iterative remapping respecting timing constraints. ISVLSI (2013)
Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis
Analytical logical effort formulation for minimum active area under delay constraints. SBCCI (2013)
Alberto Wiltgen, Kim A. Escobar, André Inácio Reis, Renato P. Ribas
Power consumption analysis in static CMOS gates. SBCCI (2013)
Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Lithography analysis of via-configurable transistor-array fabrics. NORCHIP (2012)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI (2012)
Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Functional composition: A new paradigm for performing logic synthesis. ISQED (2012)
Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Design-oriented delay model for CMOS inverter. SBCCI (2012)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. 52 (9-10) (2012)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
KL-cut based digital circuit remapping. NORCHIP (2012)
Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops (2011)
Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI (2011)
Thiago Figueiro, Renato P. Ribas, André Inácio Reis
Constructive AIG optimization considering input weights. ISQED (2011)
Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI (2011)
Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis
Contributions to the evaluation of ensembles of combinational logic gates. Microelectron. J. 42 (2) (2011)
Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
Self-checking test circuits for latches and flip-flops. IOLTS (2011)
Thiago Figueiro, Renato P. Ribas, André Inácio Reis
Constructive AIG optimization through functional composition. ARCS Workshops (2011)
Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll
Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops (2011)
Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD (2011)
Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov
Ring oscillators for functional and delay test of latches and flip-flops. SBCCI (2011)
Renato P. Ribas, André Inácio Reis, André Ivanov
Performance and functional test of flip-flops using ring oscillator structure. IDT (2011)
Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas
Transistor sizing in lithography-aware regular fabrics. SBCCI (2011)
Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis
SwitchCraft: a framework for transistor network design. SBCCI (2010)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Transistor network restructuring against NBTI degradation. Microelectron. Reliab. 50 (9-11) (2010)
Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas
Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. Microelectron. Reliab. 50 (9-11) (2010)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. 6 (1) (2010)
Carlos Eduardo Klock, Renato Perez Ribas, André Inácio Reis
Karma: um ambiente para o aprendizado de síntese de funções Booleanas. Revista Brasileira de Informática na Educ. 18 (2) (2010)
Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis
Boolean factoring with multi-objective goals. ICCD (2010)
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. 41 (4) (2010)
Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis
Improvements on the detection of false paths by using unateness and satisfiability. SBCCI (2010)
Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. DATE (2010)
Renato P. Ribas, Simone Bavaresco, Marcelo Lubaszewski, André Inácio Reis
Efficient Test Circuit to Qualify Logic Cells. ISCAS (2009)
André Inácio Reis, Roner G. Fabris
What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists. SBCCI (2009)
Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas
CMOS logic gate performance variability related to transistor network arrangements. Microelectron. Reliab. 49 (9-11) (2009)
Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS (2009)
Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis
Switch level optimization of digital CMOS gate networks. ISQED (2009)
Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED (2008)
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI (2008)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI (2007)
Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider
A comparative study of CMOS gates with minimum transistor stacks. SBCCI (2007)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS (2007)
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI (2007)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

André Inácio Reis