Felipe S. Marques

Publication Activity (10 Years)

Years Active: 2005-2021
Publications (10 Years): 10

Top Topics

Boolean Satisfiability

Differential Power Analysis

Top Venues

Publications

Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. ACM Trans. Design Autom. Electr. Syst. 26 (2) (2021)
Maicon Schneider Cardoso, Andrei A. O. Bubolz, Jordi Cortadella, Leomar Rosa, Felipe S. Marques
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability. ISCAS (2020)
Vitor G. Lima, Guilherme Paim, Leandro M. G. Rocha, Leomar S. da Rosa Jr., Felipe S. Marques, Eduardo A. C. da Costa, Vinicius V. Camargo, Rafael Soares, Sergio Bampi
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. ISCAS (2019)
Vitor G. Lima, Plinio Finkenauer, Vinicius V. Camargo, Felipe S. Marques, Leomar R. Junior, Rafael Iankowski Soares
A Novel Sizing Method Aiming Security Against Differential Power Analysis. ICECS (2018)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques
Area-Aware Design of Static CMOS Complex Gates. NEWCAS (2018)
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS (2017)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.
Post-processing of supergate networks aiming cell layout optimization. ISCAS (2017)
Gustavo H. Smaniotto, Joao J. da S. Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS (2016)
Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS (2016)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI (2014)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Transistor-level optimization of CMOS complex gates. LASCAS (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI (2012)
Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis
Improvements on the detection of false paths by using unateness and satisfiability. SBCCI (2010)
Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. DATE (2010)
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI (2007)
Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
Fast disjoint transistor networks from BDDs. SBCCI (2006)
Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI (2005)