Vinicius N. Possani

Publication Activity (10 Years)

Years Active: 2012-2022
Publications (10 Years): 10

Top Topics

Highly Non Linear

Logic Synthesis

Heuristic Search

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
Majority-based Design Flow for AQFP Superconducting Family. DATE (2022)
Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
LUT-Based Optimization For ASIC Design Flow. DAC (2021)
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37 (3) (2020)
Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
SAT-Sweeping Enhanced for Logic Synthesis. DAC (2020)
Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI (2018)
Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
Unlocking fine-grain parallelism for AIG rewriting. ICCAD (2018)
Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas
Binary adder circuit design using emerging MIGFET devices. ISQED (2017)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (9) (2017)
Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS (2016)
Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI (2014)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI (2013)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Transistor-level optimization of CMOS complex gates. LASCAS (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI (2012)