Felipe de Souza Marques

Publication Activity (10 Years)

Years Active: 2007-2022
Publications (10 Years): 9

Top Topics

Design Methodology

Admissible Heuristics

Power Dissipation

Routing Algorithm

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Julio Saraçol Domingues Júnior, Leomar Soares da Rosa Jr., Felipe de Souza Marques
Migortho: A Design Automation Flow for QCA Circuits. IEEE Des. Test 39 (2) (2022)
Stéphano M. M. Gonçalves, Leomar S. da Rosa Jr., Felipe de Souza Marques
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Julio Saraçol Domingues, Leomar Soares da Rosa, Felipe de Souza Marques
A Straightforward Methodology for QCA Circuits Design. SBCCI (2020)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques
Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs (10) (2018)
Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe de Souza Marques
A survey of path search algorithms for VLSI detailed routing. ISCAS (2017)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao J. da S. Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques
Transistor placement strategies for non-series-parallel cells. MWSCAS (2017)
Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques
Physical design of supergate cells aiming geometrical optimizations. MWSCAS (2016)
Maicon Schneider Cardoso, Regis Zanandrea, Renato Souza de Souza, Joao Junior da Silva Machado, Leomar Soares da Rosa Jr., Felipe de Souza Marques
Topological characteristics of logic networks generated by a graph-based methodology. LASCAS (2016)
Maicon Schneider Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques
Evaluating Geometric Aspects of Non-Series-Parallel Cells. SBCCI (2015)
Stephano Machado Moreira Goncalves, Leomar Soares da Rosa Jr., Felipe de Souza Marques
A new general purpose line probe routing algorithm. ICECS (2014)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI (2013)
Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis
SwitchCraft: a framework for transistor network design. SBCCI (2010)
Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED (2008)
Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider
A comparative study of CMOS gates with minimum transistor stacks. SBCCI (2007)