Vinicius Callegaro

Publication Activity (10 Years)

Years Active: 2010-2019
Publications (10 Years): 3

Top Topics

Generation Method

Logic Synthesis

Timing Constraints

Boolean Functions

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (5) (2018)
Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5 (2) (2015)
Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
SOP based logic synthesis for memristive IMPLY stateful logic. ICCD (2015)
Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS (2015)
Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis
Read-polarity-once Boolean functions. SBCCI (2013)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI (2013)
Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Transistor-level optimization of CMOS complex gates. LASCAS (2013)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Iterative remapping respecting timing constraints. ISVLSI (2013)
Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI (2012)
Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
KL-cut based digital circuit remapping. NORCHIP (2012)
Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI (2011)
Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI (2011)
Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis
Contributions to the evaluation of ensembles of combinational logic gates. Microelectron. J. 42 (2) (2011)
Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis
SwitchCraft: a framework for transistor network design. SBCCI (2010)