Paulo F. Butzen

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 44

Top Topics

Reliability Analysis

Top Venues

Publications

Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Extending Multilevel ALS to Design ATMRs. LASCAS (2024)
Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen
Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation. LATS (2024)
Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis
An Improved method to join BDDs for incompletely specified Boolean functions. ISCAS (2023)
Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. J. Electron. Test. 39 (4) (2023)
Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
Effect of Unique Table Implementation in the Performance of BDD Packages. SBCCI (2023)
Cleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra, Paulo F. Butzen, Cristina Meinhardt
A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures. SBCCI (2023)
Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI (2023)
Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
ATMR design by construction based on two-level ALS. SBCCI (2023)
Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis
Possible Reductions to Generate circuits from BDDs. ISVLSI (2022)
Matheus F. Pontes, Ingrid F. V. Oliveira, Rafael B. Schvittz, Leomar S. Rosa, Paulo F. Butzen
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. ISCAS (2022)
Cesar de S. Dias, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen
A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (4) (2022)
Clayton R. Farias, Rafael B. Schvittz, Tiago R. Balen, Paulo F. Butzen
Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method. LATS (2022)
Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen
Optimizing machine learning logic circuits with constant signal propagation. Integr. 87 (2022)
Guilherme B. Manske, Clayton R. Farias, Paulo F. Butzen, Leomar S. da Rosa
A Fast Approximate Function Generation Method to ATMR Architecture. LASCAS (2022)
Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, S. Leomar Rosa, Paulo F. Butzen, Rafael Iankowski Soares
Fault Tolerance Evaluation of Different Majority Voter Designs. ISCAS (2022)
Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt
Soft Error Sensibility Window at FinFET DICE SRAM. LASCAS (2021)
Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR (2021)
Tiago R. Balen, Carlos J. Gonzalez, Ingrid F. V. Oliveira, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. de Aguiar, Marcilei A. Guazzelli, Nilberto H. Medina, Paulo F. Butzen
Reliability Evaluation of Voters for Fault Tolerant Approximate Systems. LATS (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE (2021)
Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis
Benchmarking Open Access VLSI Partitioning Tools. LASCAS (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR (2020)
Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis
Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. ICCAD (2020)
Cleiton Magano Marques, Cristina Meinhardt, Paulo F. Butzen
Soft Error Reliability of SRAM cells during the three operation states. LATS (2020)
Rafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. ITC (2020)
Jorge Ferreira, Paulo F. Butzen, Cristina Meinhardt, Ricardo A. L. Reis
FBM: A Simple and Fast Algorithm for Placement Legalization. ICECS (2019)
Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. VLSI-SoC (Selected Papers) (2019)
Marcelo Danigno, Paulo F. Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça, Ricardo Augusto da Luz Reis
Proposal and Evaluation of Pin Access Algorithms for Detailed Routing. ICECS (2019)
Cesar de S. Dias, Paulo F. Butzen
A Novel SPICE Model of Memristive Devices with Threshold Current Based Control. SBCCI (2018)
Roberto B. Almeida, Paulo F. Butzen, Cristina Meinhardt
16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects. SBCCI (2018)
Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, S. Leomar Rosa, Denis Teixeira Franco
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. ICECS (2018)
Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt, Denis Teixeira Franco, Lirida A. B. Naviner, Leomar S. da Rosa, Paulo F. Butzen
Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS (2018)
Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. ICECS (2018)
Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fabio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt
Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectron. Reliab. (2018)
Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen
Fault masking ratio analysis of majority voters topologies. LATS (2018)
Gabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco
Exploring BDDs to reduce test pattern set. LATS (2017)
Fabio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm. ICECS (2016)
Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, Y. Wang, Hao Cai
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. Microelectron. Reliab. 64 (2016)
Eduardo Liebl, Cristina Meinhardt, Paulo F. Butzen
Reliability analysis of majority voters under permanent faults. LATS (2016)
Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner, Cristina Meinhardt, Paulo F. Butzen
Inserting permanent fault input dependence on PTM to improve robustness evaluation. SBCCI (2016)
Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt, Paulo F. Butzen
A probabilistic model for stuck-on faults in combinational logic gates. LATS (2016)
Rafael B. Schivittz, Cristina Meinhardt, Paulo F. Butzen
An evaluation of BTI degradation of 32nm standard cells. ICECS (2015)
Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas
Automatic circuit generation for sequential logic debug. ICECS (2015)
Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC (2015)
Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
A methodology to evaluate the aging impact on flip-flops performance. SBCCI (2013)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. 53 (9-11) (2013)
Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53 (9-11) (2013)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. 52 (9-10) (2012)
John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI (2011)
Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD (2011)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Transistor network restructuring against NBTI degradation. Microelectron. Reliab. 50 (9-11) (2010)
Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. 6 (1) (2010)
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. 41 (4) (2010)
Paulo F. Butzen, André Inácio Reis, Renato P. Ribas
Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS (2009)
John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim
An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC (2008)
Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI (2008)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI (2007)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS (2007)
Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas
Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI (2007)