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Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits.

Paulo F. ButzenVinícius Dal BemAndré Inácio ReisRenato P. Ribas
Published in: J. Low Power Electron. (2010)
Keyphrases
  • high speed
  • delay insensitive
  • lower bound
  • analog vlsi