Alan Mishchenko

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 66

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DAC

DATE

ICCAD

Publications

Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
Scalable Sequential Optimization Under Observability Don't Cares. DATE (2024)
Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton
Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR (2024)
Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli
An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization. ISCAS (2024)
Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury
High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC (2024)
Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. ICCAD (2023)
Yingjie Li, Mingju Liu, Mark Ren, Alan Mishchenko, Cunxi Yu
DAG-aware Synthesis Orchestration. CoRR (2023)
Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu
Improving Standard-Cell Design Flow using Factored Form Optimization. DAC (2023)
Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
Scalable Sequential Optimization Under Observability Don't Cares. CoRR (2023)
Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE (2023)
Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu
Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. CoRR (2023)
Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
Improving LUT-based optimization for ASICs. DAC (2022)
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC (2022)
Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
LUT-Based Optimization For ASIC Design Flow. DAC (2021)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE (2021)
He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
Deep Integration of Circuit Simulator and SAT Solver. DAC (2021)
He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko
A Circuit-Based SAT Solver for Logic Synthesis. ICCAD (2021)
Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Chang Meng, Weikang Qian, Alan Mishchenko
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set. DAC (2020)
Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
Simulation-Guided Boolean Resubstitution. CoRR (2020)
Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) (2020)
Alan Mishchenko
Keynote III: Boolean Logic Networks for Machine Learning. ISMVL (2020)
Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jonata T. Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR (2020)
Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8 (2020)
Xuegong Zhou, Lingli Wang, Alan Mishchenko
Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm. IEEE Trans. Computers 69 (9) (2020)
Satrajit Chatterjee, Alan Mishchenko
Circuit-Based Intrinsic Methods to Detect Overfitting. ICML (2020)
Heinz Riener, Alan Mishchenko, Mathias Soeken
Exact DAG-Aware Rewriting. DATE (2020)
Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
SAT-Sweeping Enhanced for Logic Synthesis. DAC (2020)
Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Scalable Boolean Methods in a Modern Synthesis Flow. DATE (2019)
Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas
Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (5) (2019)
Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE (2019)
Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
Scaling-up ESOP Synthesis for Quantum Compilation. ISMVL (2019)
Xuegong Zhou, Lingli Wang, Alan Mishchenko
Fast Adjustable NPN Classification Using Generalized Symmetries. ACM Trans. Reconfigurable Technol. Syst. 12 (2) (2019)
Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis
Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI (2019)
Satrajit Chatterjee, Alan Mishchenko
Circuit-Based Intrinsic Methods to Detect Overfitting. CoRR (2019)
Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
Logic Optimization of Majority-Inverter Graphs. MBMV (2019)
Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC (2019)
Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
SAT based exact synthesis using DAG topology families. DAC (2018)
Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton
SAT-based area recovery in structural technology mapping. ASP-DAC (2018)
Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
Unlocking fine-grain parallelism for AIG rewriting. ICCAD (2018)
Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli
Practical exact synthesis. DATE (2018)
Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko
Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (9) (2018)
Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli
Pairs of majority-decomposing functions. Inf. Process. Lett. 139 (2018)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Improvements to boolean resynthesis. DATE (2018)
Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
Efficient computation of ECO patch functions. DAC (2018)
Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski
Rewriting Environment for Arithmetic Circuit Verification. LPAR (2018)
Wenyi Feng, Jonathan W. Greene, Alan Mishchenko
Improving FPGA Performance with a S44 LUT Structure. FPGA (2018)
Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
Canonical computation without canonical representation. DAC (2018)
Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko
SAT-Based Fault Equivalence Checking in Functional Safety Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (12) (2018)
Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko
Fast Adjustable NPN Classification using Generalized Symmetries. FPL (2018)
Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton
Property directed reachability with word-level abstraction. FMCAD (2017)
Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko
Reduction of Quantum Cost by Making Temporary Changes to the Function. IEICE Trans. Inf. Syst. (7) (2017)
Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
Fast-extract with cube hashing. ASP-DAC (2017)
Gianpiero Cabodi, Paolo Camurati, Alan Mishchenko, Marco Palena, Paolo Pasini
SAT solver management strategies in IC3: an experimental approach. Formal Methods Syst. Des. 50 (1) (2017)
Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
Enabling exact delay synthesis. ICCAD (2017)
Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
Busy man's synthesis: Combinational delay optimization with SAT. DATE (2017)
Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton
2QBF: Challenges and Solutions. SAT (2016)
Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl
Clauses Versus Gates in CEGAR-Based 2QBF Solving. AAAI Workshop: Beyond NP (2016)
Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT (2016)
Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD (2016)
Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
Fast hierarchical NPN classification. FPL (2016)
Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton
Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD (2016)
Hamid Savoj, Alan Mishchenko, Robert K. Brayton
m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (6) (2016)
Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene
Technology Mapping into General Programmable Cells. FPGA (2015)
Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton
Component-Based Design by Solving Language Equations. Proc. IEEE 103 (11) (2015)
Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko
Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops (2015)
Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko
Threshold Logic Synthesis Based on Cut Pruning. ICCAD (2015)
Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
Improved carry chain mapping for the VTR flow. FPT (2015)
Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli
Exploiting Circuit Duality to Speed up SAT. ISVLSI (2015)
Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko
Incremental ATPG methods for multiple faults under multiple fault models. ISQED (2015)
Masahiro Fujita, Alan Mishchenko
Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC (2014)
Hamid Savoj, Alan Mishchenko, Robert K. Brayton
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (2) (2014)
Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne
Constrained interpolation for guided logic synthesis. ICCAD (2014)
Masahiro Fujita, Alan Mishchenko
Logic synthesis and verification on fixed topology. VLSI-SoC (2014)
Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB (2014)
Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC (2014)
Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla
GLA: gate-level abstraction revisited. DATE (2013)
Zheng Huang, Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko
Fast Boolean matching based on NPN classification. FPT (2013)
Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma
A semi-canonical form for sequential AIGs. DATE (2013)
Anton Belov, Huan Chen, Alan Mishchenko, João Marques-Silva
Core minimization in SAT-based abstraction. DATE (2013)
Marco Palena, Gianpiero Cabodi, Alan Mishchenko
Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3. DIFTS@FMCAD (2013)
Niklas Eén, Alan Mishchenko
A Fast Reparameterization Procedure. DIFTS@FMCAD (2013)
Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
Mapping into LUT structures. DATE (2012)
Wenlong Yang, Lingli Wang, Alan Mishchenko
Lazy man's logic synthesis. ICCAD (2012)
Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets
Delay optimization using SOP balancing. ICCAD (2011)
Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD (2011)
Niklas Eén, Alan Mishchenko, Robert K. Brayton
Efficient implementation of property directed reachability. FMCAD (2011)
Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu
Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL (2010)
Robert K. Brayton, Alan Mishchenko
ABC: An Academic Industrial-Strength Verification Tool. CAV (2010)
Dmitri B. Strukov, Alan Mishchenko
Monolithically stackable hybrid FPGA. DATE (2010)
Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang
To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59 (4) (2010)
Niklas Eén, Alan Mishchenko, Nina Amla
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. FMCAD (2010)
Niklas Eén, Alan Mishchenko, Nina Amla
A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction CoRR (2010)
Alan Mishchenko, Robert K. Brayton, Stephen Jang
Global delay optimization using structural choices. FPGA (2010)
Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton
Combinational techniques for sequential equivalence checking. FMCAD (2010)
Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko
Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15 (3) (2010)

Alan Mishchenko.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Alan Mishchenko