Rajit Manohar

ORCID

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 52

Top Venues

ASYNC

CoRR

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, Maya B. Gokhale
Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine. DATE (2024)
Esteban Ramos, Robert Soulé, Peter Alvaro, Pietro Bressana, Edmund Chen, Uri Cummings, Rui Li, James Tsai, Rajit Manohar
Split gRPC: An Isolation Architecture for RPC Software Stacks. APSys (2024)
Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury
High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC (2024)
Karthi Srinivasan, Yoram Moses, Rajit Manohar
Opportunistic Mutual Exclusion. CoRR (2023)
Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Muhammed Ugur, Oliver Ye, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee
SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing. ISCA (2023)
Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Oliver Ye, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee
A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing. CoRR (2023)
Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Ján Veselý, Nick Lindsay, Michael Wu, Lenny Khazan, Raghavendra Pradyumna Pothukuchi, Rajit Manohar, Abhishek Bhattacharjee
HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro 43 (3) (2023)
Prafull Purohit, Johannes Leugering, Rajit Manohar
An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. ASYNC (2023)
Thomas Jagielski, Rajit Manohar, Jaijeet Roychowdhury
FPIM: Field-Programmable Ising Machines for Solving SAT. CoRR (2023)
Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR (2023)
Karthi Srinivasan, Yoram Moses, Rajit Manohar
Opportunistic Mutual Exclusion. ASYNC (2023)
Rajit Manohar, Yoram Moses
Timed Signalling Processes. ASYNC (2023)
Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR (2023)
Xiang Wu, Rajit Manohar
Verification-Driven Design for Asynchronous VLSI. ASYNC (2023)
Abhishek Bhattacharjee, Rajit Manohar
HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HCS (2022)
Rajit Manohar
Hardware/software Co-design for Neuromorphic Systems. CICC (2022)
Ruslan Dashkin, Rajit Manohar
General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (10) (2022)
Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali
SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity. ASP-DAC (2022)
Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher
A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IPDPS Workshops (2022)
Prafull Purohit, Rajit Manohar
Hierarchical Token Rings for Address-Event Encoding. ASYNC (2021)
Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee
Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro 41 (3) (2021)
Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé
Zerializer: towards zero-copy serialization. HotOS (2021)
Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali
An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test 38 (2) (2021)
Rui Li, Lincoln Berkley, Yihang Yang, Rajit Manohar
Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. ASYNC (2021)
Samira Ataei, Rajit Manohar
Shared-Staticizer for Area-Efficient Asynchronous Circuits. ASYNC (2020)
Rajit Manohar
Exact Timing Analysis for Asynchronous Circuits With Multiple Periods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee
Hardware-Software Co-Design for Brain-Computer Interfaces. ISCA (2020)
Yihang Yang, Jiayuan He, Rajit Manohar
Dali: A Gridded Cell Placement Flow. ICCAD (2020)
Nathan Manohar, Peter Manohar, Rajit Manohar
HABIT: Hardware-Assisted Bluetooth-based Infection Tracking. IACR Cryptol. ePrint Arch. 2020 (2020)
Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. ASYNC (2020)
Ned Bingham, Rajit Manohar
A Systematic Approach for Arbitration Expressions. IEEE Trans. Circuits Syst. (12) (2020)
Ned Bingham, Rajit Manohar
QDI Constant-Time Counters. IEEE Trans. Very Large Scale Integr. Syst. 27 (1) (2019)
Ned Bingham, Rajit Manohar
Self-Timed Adaptive Digit-Serial Addition. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Alexander Neckar, Sam Fok, Ben Varkey Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen
Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. Proc. IEEE 107 (1) (2019)
Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali
SPRoute: A Scalable Parallel Negotiation-based Global Router. ICCAD (2019)
Samira Ataei, Rajit Manohar
AMC: An Asynchronous Memory Compiler. ASYNC (2019)
Nitish Kumar Srivastava, Rajit Manohar
Operation-Dependent Frequency Scaling Using Desynchronization. IEEE Trans. Very Large Scale Integr. Syst. 27 (4) (2019)
Rajit Manohar, Yoram Moses
Asynchronous Signalling Processes. ASYNC (2019)
Saber Moradi, Rajit Manohar
The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. CoRR (2018)
Wenmian Hua, Rajit Manohar
Exact Timing Analysis for Asynchronous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (1) (2018)
Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis P. Tsividis
A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. IEEE J. Solid State Circuits 53 (2) (2018)
Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA (2017)
Tayyar Rzayev, Saber Moradi, David H. Albonesi, Rajit Manohar
DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks. IJCNN (2017)
Asa Dan, Rajit Manohar, Yoram Moses
On Using Time Without Clocks via Zigzag Causality. CoRR (2017)
Saber Moradi, Sunil A. Bhave, Rajit Manohar
Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28 nm CMOS Process. CoRR (2017)
Tayyar Rzayev, David H. Albonesi, François Guimbretière, Rajit Manohar, Jaeyeon Kihm
Toolbox for exploration of energy-efficient event processors for human-computer interaction. ISPASS (2017)
Yu Chen, Rajit Manohar, Yannis P. Tsividis
Design of tunable digital delay cells. CICC (2017)
Rajit Manohar, Yoram Moses
The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. ASYNC (2017)
Saber Moradi, Sunil A. Bhave, Rajit Manohar
Energy-efficient hybrid CMOS-NEMS LIF neuron circuit in 28 nm CMOS process. SSCI (2017)
Asa Dan, Rajit Manohar, Yoram Moses
On Using Time Without Clocks via Zigzag Causality. PODC (2017)
Sandra J. Jackson, Rajit Manohar
Gradual Synchronization. ASYNC (2016)
Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar
Timing Driven Placement for Quasi Delay-Insensitive Circuits. ASYNC (2015)
Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
AES Hardware-Software Co-design in WSN. ASYNC (2015)
Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate
Preventing glitches and short circuits in high-level self-timed chip specifications. PLDI (2015)
Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar
Automatic obfuscated cell layout for trusted split-foundry design. HOST (2015)
Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar
Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications. ISCAS (2015)
Rajit Manohar
Comparing Stochastic and Deterministic Computing. IEEE Comput. Archit. Lett. 14 (2) (2015)
Rajit Manohar, Yoram Moses
Analyzing Isochronic Forks with Potential Causality. ASYNC (2015)
Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar
ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. ISQED (2014)
François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar
An asymmetric dual-processor architecture for low-power information appliances. ACM Trans. Embed. Comput. Syst. 13 (4) (2014)
Benjamin Z. Tang, Sunil A. Bhave, Rajit Manohar
Low Power Asynchronous VLSI with NEM Relays. ASYNC (2014)
Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC (2014)
Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar
Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays. CHI (2014)
Stephen Longfield Jr., Rajit Manohar
Removing concurrency for rapid functional verification. ICCAD (2014)
Stephen Longfield Jr., Rajit Manohar
Inverting Martin Synthesis for Verification. ASYNC (2013)
Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, Rajit Manohar
Neural spiking dynamics in asynchronous digital circuits. IJCNN (2013)
Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
A split-foundry asynchronous FPGA. CICC (2013)
Jonathan Tse, Benjamin Hill, Rajit Manohar
A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. ASYNC (2013)
Saber Moradi, Nabil Imam, Rajit Manohar, Giacomo Indiveri
A memory-efficient routing method for large-scale spiking neural networks. ECCTD (2013)
Robert Karmazin, Carlos Tadeo Ortega Otero, Rajit Manohar
cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. ASYNC (2013)
Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. ASYNC (2012)
Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. IET Circuits Devices Syst. 6 (1) (2012)
Basit Riaz Sheikh, Rajit Manohar
An Asynchronous Floating-Point Multiplier. ASYNC (2012)
John V. Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez-Icaza, Andrew Cassidy, Shyamal Chandra, Steven K. Esser, Nabil Imam, William P. Risk, Daniel Ben Dayan Rubin, Rajit Manohar, Dharmendra S. Modha
Building block of a programmable neuromorphic substrate: A digital neurosynaptic core. IJCNN (2012)
Benjamin Z. Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar
A Low Power Asynchronous GPS Baseband Processor. ASYNC (2012)
Nabil Imam, Rajit Manohar
Address-Event Communication Using Token-Ring Mutual Exclusion. ASYNC (2011)
Paul Merolla, John V. Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha
A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm. CICC (2011)
Basit Riaz Sheikh, Rajit Manohar
Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits. ACM J. Emerg. Technol. Comput. Syst. 7 (4) (2011)
Christopher LaFrieda, Benjamin Hill, Rajit Manohar
An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. ASYNC (2010)
Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
Static Power Reduction Techniques for Asynchronous Circuits. ASYNC (2010)
Basit Riaz Sheikh, Rajit Manohar
An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder. ASYNC (2010)
Christopher LaFrieda, Rajit Manohar
Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. ASYNC (2009)
Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra J. Jackson, Rajit Manohar
Variability in 3-D integrated circuits. CICC (2008)
Qing Zhao, Rajit Manohar, Robert J. Ulman, Venugopal V. Veeravalli
Resource-Constrained Signal Processing, Communications, and Networking [From the Guest Editors]. IEEE Signal Process. Mag. 24 (3) (2007)
Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. DSN (2007)
Alyssa B. Apsel, Rajit Manohar, Alain J. Martin
Analog and asynchronous variation-aware circuits. ICECS (2007)
Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. ASYNC (2006)
Rajit Manohar
Reconfigurable Asynchronous Logic. CICC (2006)
David Fang, Filipp Akopyan, Rajit Manohar
Self-Timed Thermally-Aware Circuits. ISVLSI (2006)
Song Peng, Rajit Manohar
Self-Healing Asynchronous Arrays. ASYNC (2006)
Song Peng, Rajit Manohar
Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI (2006)
Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari
Mapping system-on-chip designs from 2-D to 3-D ICs. ISCAS (3) (2005)
Song Peng, Rajit Manohar
Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. ICCD (2005)
Song Peng, David Fang, John Teifel, Rajit Manohar
Automated synthesis for asynchronous FPGAs. FPGA (2005)
Song Peng, Rajit Manohar
Efficient Failure Detection in Pipelined Asynchronous Circuits. DFT (2005)
Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. ASYNC (2005)
David Fang, John Teifel, Rajit Manohar
A High-Performance Asynchronous FPGA: Test Results. FCCM (2005)
John Teifel, Rajit Manohar
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. ASYNC (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

Rajit Manohar